Patents by Inventor Yu-Nan Shih
Yu-Nan Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10644662Abstract: A amplifier circuit in some embodiment includes a differential amplifier have a pair of current sources. Each of the current sources includes two or more current-generating transistors and respective switching transistors, which can be turned on and off by a gain input code to tune the gain of the amplifier. A common-mode controller includes a similar pair of current sources as the differential amplifier. The common mode controller receives a common-mode signal of the input signal and a common-mode gain input code, and maintains the common-mode gain of the amplifier circuit when the differential gain changes. The amplifier circuit is switchable between a buffer mode and an equalizer mode.Type: GrantFiled: November 29, 2017Date of Patent: May 5, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Chun Yang, Wei Chih Chen, Yu-Nan Shih
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Publication number: 20190165744Abstract: A amplifier circuit in some embodiment includes a differential amplifier have a pair of current sources. Each of the current sources includes two or more current-generating transistors and respective switching transistors, which can be turned on and off by a gain input code to tune the gain of the amplifier. A common-mode controller includes a similar pair of current sources as the differential amplifier. The common mode controller receives a common-mode signal of the input signal and a common-mode gain input code, and maintains the common-mode gain of the amplifier circuit when the differential gain changes. The amplifier circuit is switchable between a buffer mode and an equalizer mode.Type: ApplicationFiled: November 29, 2017Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Chun Yang, Wei Chih Chen, Yu-Nan Shih
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Patent number: 10270454Abstract: A clock and data recovery (CDR) device is disclosed. The CDR device comprises a sensing unit and an interpolator. The sensing unit is configured to detect a data center, a left data edge and a right data edge of a data on a data stream in a communication system, using a set of thresholds, in response to a first clock signal for sampling the data center, a second clock signal for sampling the left data edge and a third clock signal for sampling the right data edge. Each of the thresholds is related to a different level among data levels of the data. The interpolator is configured to generate the first clock signal based on information on the data center, and generate the second clock signal and the third clock signal based on information on the left and right data edges.Type: GrantFiled: December 20, 2016Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventor: Yu-Nan Shih
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Patent number: 10037969Abstract: An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.Type: GrantFiled: August 14, 2017Date of Patent: July 31, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yu-Nan Shih
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Publication number: 20180152285Abstract: A clock and data recovery (CDR) device is disclosed. The CDR device comprises a sensing unit and an interpolator. The sensing unit is configured to detect a data center, a left data edge and a right data edge of a data on a data stream in a communication system, using a set of thresholds, in response to a first clock signal for sampling the data center, a second clock signal for sampling the left data edge and a third clock signal for sampling the right data edge. Each of the thresholds is related to a different level among data levels of the data. The interpolator is configured to generate the first clock signal based on information on the data center, and generate the second clock signal and the third clock signal based on information on the left and right data edges.Type: ApplicationFiled: December 20, 2016Publication date: May 31, 2018Inventor: YU-NAN SHIH
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Publication number: 20170345791Abstract: An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.Type: ApplicationFiled: August 14, 2017Publication date: November 30, 2017Inventor: Yu-Nan Shih
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Patent number: 9741687Abstract: An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.Type: GrantFiled: May 11, 2016Date of Patent: August 22, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yu-Nan Shih
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Patent number: 9564900Abstract: A device is disclosed that includes a driver circuit and a control circuit. The driver circuit is configured to provide an output signal according to an input signal, and operated with a first voltage and a second voltage. The driver circuit includes a pull up unit and a pull down unit configured to pull up and pull down a voltage level of the output signal, respectively. The control circuit is configured to selectively enable one of the pull up unit and the pull down unit according to the input signal, so as to adjust the voltage level of the output signal. The control circuit is further configured to drive the enabled one of the pull up unit and the pull down unit in a voltage mode or a current mode selectively according to the voltage level of the output signal, the first voltage and the second voltage.Type: GrantFiled: April 16, 2015Date of Patent: February 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ying-Yu Hsu, Chien-Chun Tsai, Yu-Nan Shih
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Patent number: 9531386Abstract: A circuit includes a first power node that carries a first supply voltage having a first voltage level and a second power node that carries a second supply voltage having a second voltage level less than the first voltage level. A voltage driver has a first plurality of transistors, an input node for an input signal, and an output node, and a current driver has a second plurality of transistors. The current driver injects or extracts an adjustment current into or out of the output node. The first plurality of transistors and the second plurality of transistors electrically couple the output node and the current driver to the first power node in response to the input signal being at a first logic state, and electrically decouple the output node and the current driver from the first power node in response to the input signal being at a second logic state.Type: GrantFiled: April 28, 2015Date of Patent: December 27, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Yu-Nan Shih
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Publication number: 20160308533Abstract: A device is disclosed that includes a driver circuit and a control circuit. The driver circuit is configured to provide an output signal according to an input signal, and operated with a first voltage and a second voltage. The driver circuit includes a pull up unit and a pull down unit configured to pull up and pull down a voltage level of the output signal, respectively. The control circuit is configured to selectively enable one of the pull up unit and the pull down unit according to the input signal, so as to adjust the voltage level of the output signal. The control circuit is further configured to drive the enabled one of the pull up unit and the pull down unit in a voltage mode or a current mode selectively according to the voltage level of the output signal, the first voltage and the second voltage.Type: ApplicationFiled: April 16, 2015Publication date: October 20, 2016Inventors: Ying-Yu HSU, Chien-Chun TSAI, Yu-Nan SHIH
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Publication number: 20160254248Abstract: An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.Type: ApplicationFiled: May 11, 2016Publication date: September 1, 2016Inventor: Yu-Nan Shih
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Patent number: 9355892Abstract: An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.Type: GrantFiled: September 9, 2013Date of Patent: May 31, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yu-Nan Shih
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Publication number: 20150229308Abstract: A circuit includes a first power node that carries a first supply voltage having a first voltage level and a second power node that carries a second supply voltage having a second voltage level less than the first voltage level. A voltage driver has a first plurality of transistors, an input node for an input signal, and an output node, and a current driver has a second plurality of transistors. The current driver injects or extracts an adjustment current into or out of the output node. The first plurality of transistors and the second plurality of transistors electrically couple the output node and the current driver to the first power node in response to the input signal being at a first logic state, and electrically decouple the output node and the current driver from the first power node in response to the input signal being at a second logic state.Type: ApplicationFiled: April 28, 2015Publication date: August 13, 2015Inventor: Yu-Nan SHIH
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Patent number: 9041439Abstract: A circuit includes a first power node at a first voltage level, a second power node at a second voltage level, a first voltage driver, a first current driver, and a control unit. The first voltage driver is configured to electrically couple a first output node to the first power node when a first input signal at the first input node is at a first logic state, and electrically couple a first output node to the second power node when the first input signal is at a second logic state. The first current driver is configured to inject or extract a first adjustment current into or out of a first output node. The control unit is configured to generate a measurement result of the first voltage level, and to set the first adjustment current according to the measurement result.Type: GrantFiled: August 30, 2013Date of Patent: May 26, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Yu-Nan Shih
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Publication number: 20150069570Abstract: An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.Type: ApplicationFiled: September 9, 2013Publication date: March 12, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Yu-Nan Shih
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Publication number: 20150061745Abstract: A circuit includes a first power node at a first voltage level, a second power node at a second voltage level, a first voltage driver, a first current driver, and a control unit. The first voltage driver is configured to electrically couple a first output node to the first power node when a first input signal at the first input node is at a first logic state, and electrically couple a first output node to the second power node when the first input signal is at a second logic state. The first current driver is configured to inject or extract a first adjustment current into or out of a first output node. The control unit is configured to generate a measurement result of the first voltage level, and to set the first adjustment current according to the measurement result.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Yu-Nan SHIH
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Patent number: 8947133Abstract: A voltage mode driver system includes a plurality of VMD cells, a plurality of auxiliary cells, a control logic and an output node. The plurality of VMD cells are configured to generate a first output. The plurality of VMD cells are configured to generate a calibrated effective resistance at different signal levels according to a calibration signal. The plurality of auxiliary cells are configured to generate a second output. The output node combines the first output and the second output into a driver output. The control logic is configured to control the plurality of auxiliary cells and the second output according to a selected level. The plurality of VMD cells may be configured to generate a calibrated effective resistance at different signal levels according to a calibration signal. A calibration component is configured to determine a voltage dependence effect and to generate a calibration signal according to the determined voltage dependence effect.Type: GrantFiled: February 4, 2013Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yu-Nan Shih
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Publication number: 20140218072Abstract: A voltage mode driver system includes a plurality of VMD cells, a plurality of auxiliary cells, a control logic and an output node. The plurality of VMD cells are configured to generate a first output. The plurality of VMD cells are configured to generate a calibrated effective resistance at different signal levels according to a calibration signal. The plurality of auxiliary cells are configured to generate a second output. The output node combines the first output and the second output into a driver output. The control logic is configured to control the plurality of auxiliary cells and the second output according to a selected level. The plurality of VMD cells may be configured to generate a calibrated effective resistance at different signal levels according to a calibration signal. A calibration component is configured to determine a voltage dependence effect and to generate a calibration signal according to the determined voltage dependence effect.Type: ApplicationFiled: February 4, 2013Publication date: August 7, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yu-Nan Shih
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Patent number: 8742799Abstract: A voltage mode driver circuit includes a plurality of VMD cells and a calibration component. The plurality of VMD cells are configured to generate a calibrated emphasis level according to a calibration signal. The calibration component is configured to determine a voltage dependence effect. Additionally, the calibration component is configured to generate the calibration signal according to the determined voltage dependence effect.Type: GrantFiled: August 30, 2012Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yu-Nan Shih
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Publication number: 20140062538Abstract: A voltage mode driver circuit includes a plurality of VMD cells and a calibration component. The plurality of VMD cells are configured to generate a calibrated emphasis level according to a calibration signal. The calibration component is configured to determine a voltage dependence effect. Additionally, the calibration component is configured to generate the calibration signal according to the determined voltage dependence effect.Type: ApplicationFiled: August 30, 2012Publication date: March 6, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yu-Nan Shih