Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.

Abstract: A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on the redistribution layer, a second encapsulation layer covering the first die and the redistribution layer, and an electrical connection terminal electrically connected to the redistribution layer. The first encapsulation layer has a first surface and a second surface different from the first surface. The first encapsulation layer surrounds a portion of the electrical connection terminal and exposes the electrical connection terminal.

Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.

Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.

Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.

Abstract: A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon.

Abstract: A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon.

Abstract: An embodiment of a stacked package assembly includes: (1) a first semiconductor device package including: (a) a semiconductor device including back and lateral surfaces; (b) a package body including an upper surface and substantially covering the back and lateral surfaces of the device; and (c) a first conductive contact adjacent to the upper surface of the body and electrically connected to the device; (2) a second semiconductor device package disposed above the upper surface of the body; (3) a conductive bump adjacent to the first contact and to the second device package; (4) a second conductive contact external to the first and the second device packages; and (5) a conductive wire electrically connecting the first and the second device packages to the second contact, a first end of the wire adjacent to the first contact and at least partially covered by the bump.

Abstract: A chip package includes a semiconductor substrate, conductive plugs and a chip. Wherein, the conductive plugs perforate the semiconductor substrate. Besides, the chip is disposed on a surface of the semiconductor substrate and electrically connected to the conductive plugs. Based on the above-described design, the chip package is capable of reducing the thermal stress problem caused by a coefficient of thermal expansion (CTE) dismatch compared with the prior art. The present invention discloses further a chip packaging process and furthermore a chip carrier and the process thereof.

Abstract: A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the tape and marks a pattern on the second surface of the wafer. There are glue residuals remained in the laser-marking pattern of the die manufactured according to the laser-marking method of the invention, and the components of the glue residuals at least include elements of silicon, carbon and oxygen.

Abstract: A stacked structure of chips including a first chip, a second chip, an insulation layer and a first conductive element is provided. The second chip is attached to the first chip, and the back surface of the second chip faces an active surface of the first chip. The second chip includes a first contact disposed on an active surface of the second chip. The insulation layer disposed on the active surface of the first chip encapsulates the second chip. The first conductive element is formed in the insulation layer for electrically connecting one end of the first conductive element to the first contact and the other end of the first conductive element exposed outside the insulation layer. A wafer structure for making the stacked structure of chips is also provided. The stacked structure of chips has no circuit carrier, hence reducing the thickness of the stacked structure.

Abstract: A fabricating method of wafer protection layers and a wafer structure are provided. The fabricating method includes providing a wafer first. The wafer includes pluralities of chips and has an active surface, a corresponding reverse surface and a plurality of pre-cut trenches on the active surface. On the active surface, pluralities of bumps are disposed. Next, a first curing-type protection layer and a pellicle are disposed over the active surface. Afterwards, the first curing-type protection layer is asked to contact the active surface. Besides, a second curing-type protection layer is disposed on the reverse surface. Afterward, the first and the second curing-type protection layer are cured. Finally, the wafer is cut through the pre-cut trenches to separate the chips from the wafer.

Abstract: A method of thinning wafer is disclosed. A wafer has an active surface and a back surface is provided. A plurality of protruding components may be disposed on the active surface. The wafer is placed in a mold and a polymeric material is formed in the mold to cover at least the active surface of the wafer. The polymeric material is cured and the mold is removed. The back surface of the wafer is ground to thin the wafer. The polymeric material is removed to expose the active surface of the wafer and the protruding components disposed on the active surface. The polymeric material is allowed to cover the active surface of the wafer and the protruding components through the mold; accordingly, the stress produced during the grinding can be distributed uniformly on the wafer, and the wafer warpage, breakage, or collapse, or the protruding component peeling can be avoided.

Abstract: A method for marking chip scale packages at the wafer level is provided. First, a positioning step is performed to determine the position of a plurality of semi-finished chip scale packages formed on a wafer. Each of the semi-finished chip scale package includes a plurality of terminals for making external electrical connections and each die has a plurality of bonding pads on an active surface thereof. The bonding pads are electrically connected to the respective terminals wherein a backside surface of the die is exposed from a surface of the respective semi-finished chip scale package. The exposed backside surface of the die is then marked by ink-jet printing. Afterward, the ink marks on the dice are cured. Finally, the wafer is diced to obtain a plurality of separated chip scale packages.

Abstract: A stacked structure of chips including a first chip, a second chip, an insulation layer and a first conductive element is provided. The second chip is attached to the first chip, and the back surface of the second chip faces an active surface of the first chip. The second chip includes a first contact disposed on an active surface of the second chip. The insulation layer disposed on the active surface of the first chip encapsulates the second chip. The first conductive element is formed in the insulation layer for electrically connecting one end of the first conductive element to the first contact and the other end of the first conductive element exposed outside the insulation layer. A wafer structure for making the stacked structure of chips is also provided. The stacked structure of chips has no circuit carrier, hence reducing the thickness of the stacked structure.

Abstract: A wafer-level method for manufacturing a chip package structure is disclosed. A wafer comprises a first surface and a second surface opposite thereto. The first surface has chip units disposed thereon to define scribe lines. An adhesive material is disposed between the first surface and the transparent glass for adhering the wafer to a transparent glass and leaving no gap between the first surface and the transparent glass. The wafer is vertically cut from the second surface corresponding to each scribe line of the first surface to the encapsulation adhesive material for forming scribe grooves, and then the second surface is coated with an encapsulation material for filling the scribe grooves. After removing the adhesive material and the transparent glass, the encapsulation material in each of the scribe grooves is vertically cut from the first surface, so as to form chip package structures.

Abstract: A method of fabricating a CMOS image sensor (CIS) package includes: providing a transparent substrate, in which the transparent substrate includes a cavity; disposing an image sensor chip in the cavity and forming a plurality of bumps between the image sensor chip and the transparent substrate, in which the image sensor chip includes a light sensitive area; forming a barrier wall between the transparent substrate and the image sensor chip, in which the barrier wall further forms a circular pattern around the light sensitive area of the image sensor chip; and forming an underfill layer between the transparent substrate and the image sensor chip for forming a package structure.

Abstract: A chip package includes a semiconductor substrate, conductive plugs and a chip. Wherein, the conductive plugs perforate the semiconductor substrate. Besides, the chip is disposed on a surface of the semiconductor substrate and electrically connected to the conductive plugs. Based on the above-described design, the chip package is capable of reducing the thermal stress problem caused by a coefficient of thermal expansion (CTE) dismatch compared with the prior art. The present invention discloses further a chip packaging process and furthermore a chip carrier and the process thereof.

Abstract: A fabricating method of wafer protection layers and a wafer structure are provided. The fabricating method includes providing a wafer first. The wafer includes pluralities of chips and has an active surface, a corresponding reverse surface and a plurality of pre-cut trenches on the active surface. On the active surface, pluralities of bumps are disposed. Next, a first curing-type protection layer and a pellicle are disposed over the active surface. Afterwards, the first curing-type protection layer is asked to contact the active surface. Besides, a second curing-type protection layer is disposed on the reverse surface. Afterward, the first and the second curing-type protection layer are cured. Finally, the wafer is cut through the pre-cut trenches to separate the chips from the wafer.

Abstract: A semiconductor wafer cassette has a first side wall, a second side wall opposite the first side wall, a front surface, and a back surface opposite the front surface. A body defines an internal bay portion with slots for vertically receiving wafers, each slot of the internal bay portion having one support slab. The body also includes two parallel legs for supporting the cassette and a handle for handling the cassette.