Patents by Inventor Yu-Ping Huang
Yu-Ping Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240161818Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.Type: ApplicationFiled: November 30, 2022Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Li-Ping Huang, Yu-Fang Chen, Chun-Yen Tseng, Tzu-Feng Chang, Chun-Chieh Chang
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Publication number: 20240130141Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Applicant: United Microelectronics Corp.Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
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Publication number: 20240112323Abstract: A method for detecting defects on a wafer including the steps of obtaining a reference image of a chip pattern formed on a reference wafer, using a computer algorithm to analyze the reference image to produce a division map for the chip pattern; setting respective thresholds for divisions of the division map, obtaining a comparison data between a test image of the chip pattern formed on a test wafer and the reference image, using the division map and the thresholds to examine the comparison data to identify a defect in the test image.Type: ApplicationFiled: November 17, 2022Publication date: April 4, 2024Applicant: United Semiconductor (Xiamen) Co., Ltd.Inventors: Yu Peng Hong, QINGRONG CHEN, Kai Ping Huang, Chin-Chun Huang, WEN YI TAN
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Patent number: 11942390Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.Type: GrantFiled: June 6, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Sheh Huang, Yu-Hsiang Chen, Chii-Ping Chen
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Publication number: 20240085753Abstract: An electrochromic composition including: a first oxidizable compound; a reducible compound; an electrolyte; and a solvent, wherein the first oxidizable compound is represented by the following formula: wherein X1, and X2 are independently substituted or unsubstituted aliphatic hydrocarbon groups, or substituted or unsubstituted aromatic hydrocarbon groups, wherein the aromatic hydrocarbon groups include: wherein each Rx is independently hydrogen, a C1-C16 alkyl group, a C1-C16 alkoxy group, a C1-C16 haloalkyl group, or halogen.Type: ApplicationFiled: February 24, 2023Publication date: March 14, 2024Inventors: Hao-Ping HUANG, Tsung-Hsien LIN, Yu-Nan LEE
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Patent number: 11929319Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.Type: GrantFiled: July 22, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
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Publication number: 20240074209Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.Type: ApplicationFiled: November 2, 2023Publication date: February 29, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jia-Rong Wu, I-Fan Chang, Rai-Min Huang, Ya-Huei Tsai, Yu-Ping Wang
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Patent number: 11915755Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.Type: GrantFiled: January 20, 2022Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang, Yu-Fang Chen
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Publication number: 20240021246Abstract: A selection circuit includes a main selection circuit and an auxiliary selection circuit. When a first voltage and a second voltage are different, the main selection circuit selects a higher one of the first voltage and the second voltage as an output voltage. When the first voltage and the second voltage are equal, the auxiliary selection circuit generates the output voltage according to the first voltage and the second voltage.Type: ApplicationFiled: May 9, 2023Publication date: January 18, 2024Applicant: eMemory Technology Inc.Inventors: Yu-Ping Huang, Chun-Hung Lin, Cheng-Da Huang
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Patent number: 11455103Abstract: A cloud secured storage system is provided in a peer-to-peer network that includes a client end and a farm end. A user file is segmented and a hash function is used for encryption to generate a plurality of data chunks together with an Information Dispersal Algorithm. The plurality of data chunks are respectively stored in a plurality of cloud servers. The plurality of cloud servers backup the plurality of data chunks as a backup file. If the data chunk in one of the plurality of cloud servers is lost, the adjacent cloud server transmits the backup file to the cloud server where the data chunk is lost. The cloud secured storage system of the present disclosure successfully stores the user file in the plurality of cloud servers to prevent cyberattacks owing to the process of file segmentation, encryption, backup file, and algorithm.Type: GrantFiled: September 17, 2020Date of Patent: September 27, 2022Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Tsung-Nan Lin, Yu-Ping Huang
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Patent number: 11074963Abstract: A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m×n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.Type: GrantFiled: April 1, 2020Date of Patent: July 27, 2021Assignee: EMEMORY TECHNOLOGY INC.Inventors: Yu-Ping Huang, Chun-Hung Lin, Cheng-Da Huang
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Publication number: 20210096753Abstract: A cloud secured storage system is provided in a peer-to-peer network that includes a client end and a farm end. A user file is segmented and a hash function is used for encryption to generate a plurality of data chunks together with an Information Dispersal Algorithm. The plurality of data chunks are respectively stored in a plurality of cloud servers. The plurality of cloud servers backup the plurality of data chunks as a backup file. If the data chunk in one of the plurality of cloud servers is lost, the adjacent cloud server transmits the backup file to the cloud server where the data chunk is lost. The cloud secured storage system of the present disclosure successfully stores the user file in the plurality of cloud servers to prevent cyberattacks owing to the process of file segmentation, encryption, backup file, and algorithm.Type: ApplicationFiled: September 17, 2020Publication date: April 1, 2021Inventors: Tsung-Nan Lin, Yu-Ping Huang
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Publication number: 20200365200Abstract: A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m×n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.Type: ApplicationFiled: April 1, 2020Publication date: November 19, 2020Inventors: Yu-Ping HUANG, Chun-Hung LIN, Cheng-Da HUANG
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Patent number: 10644911Abstract: A multi-level pulse-amplitude modulation receiver system includes an analog equalizer, a digital equalizer, an automatic level tracking engine and an automatic gain controller. The analog equalizer and the automatic gain controller perform signal compensation on a multi-bit quasi-attenuation signal to generate a multi-level compensation signal. The digital equalizer receives the multi-level compensation signal, the positive threshold voltage and the negative threshold voltage, and thereby converts the multi-level compensation signal into a plurality of digital data. The automatic level tracking engine uses the digital data to generate a positive threshold voltage, a negative threshold voltage, at least two positive DC level voltages, and at least two negative DC level voltages, and the positive threshold voltage is an average of the two positive DC level voltages to avoid the nonlinear effect of the analog front end.Type: GrantFiled: August 22, 2019Date of Patent: May 5, 2020Assignee: National Chiao Tung UniversityInventors: Wei-Zen Chen, Chia-Tse Hung, Yu-Ping Huang, Yao-Chia Liu
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Patent number: 9407474Abstract: A phase detecting device and a clock data recovery circuit are provided. The phase detecting device includes a decision feedback equalizer having first and second sample-hold sub-circuits, an edge detector having a third sample-hold sub-circuit, a first XOR gate, and a second XOR gate. The first sample-hold sub-circuit, the second sample-hold sub-circuit and the third sample-hold sub-circuit obtain first sample data, second sample data and transition data, respectively. The first XOR gate executes an XOR operation for the first sample data and the transition data to generate first clock phase shift information. The second XOR gate executes the XOR operation for the second sample data and the transition data to generate second clock phase shift information. Therefore, high-frequency noise disturbance generated from conventional clock data recovery circuit and decision feedback equalizer can be avoided.Type: GrantFiled: September 16, 2015Date of Patent: August 2, 2016Assignee: National Chiao Tung UniversityInventors: Wei-Zen Chen, Yu-Ping Huang, Yau-Chia Liu, Zheng-Hao Hong
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Publication number: 20160080178Abstract: A phase detecting device and a clock data recovery circuit are provided. The phase detecting device includes a decision feedback equalizer having first and second sample-hold sub-circuits, an edge detector having a third sample-hold sub-circuit, a first XOR gate, and a second XOR gate. The first sample-hold sub-circuit, the second sample-hold sub-circuit and the third sample-hold sub-circuit obtain first sample data, second sample data and transition data, respectively. The first XOR gate executes an XOR operation for the first sample data and the transition data to generate first clock phase shift information. The second XOR gate executes the XOR operation for the second sample data and the transition data to generate second clock phase shift information. Therefore, high-frequency noise disturbance generated from conventional clock data recovery circuit and decision feedback equalizer can be avoided.Type: ApplicationFiled: September 16, 2015Publication date: March 17, 2016Inventors: Wei-Zen Chen, Yu-Ping Huang, Yau-Chia Liu, Zheng-Hao Hong
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Patent number: 8957660Abstract: The present invention discloses a current balance circuit for a multiphase DC-DC converter. The current balance circuit comprises a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels, a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals, and a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals.Type: GrantFiled: September 11, 2012Date of Patent: February 17, 2015Assignee: Anpec Electronics CorporationInventors: Ke-Horng Chen, Yueh-Lung Kuo, Chih-Heng Su, Yi-Ping Su, Yu-Ping Huang, Yu-Huei Lee
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Publication number: 20130293203Abstract: The present invention discloses a current balance circuit for a multiphase DC-DC converter. The current balance circuit comprises a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels, a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals, and a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals.Type: ApplicationFiled: September 11, 2012Publication date: November 7, 2013Applicant: ANPEC ELECTRONICS CORPORATIONInventors: Ke-Horng Chen, Yueh-Lung Kuo, Chih-Heng Su, Yi-Ping Su, Yu-Ping Huang, Yu-Huei Lee
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Patent number: 6586146Abstract: A method of figuring an exposure energy. A required exposure energy is calculated according to a critical dimension (CD) of an exposing layer. A first CD deviation is obtained from a layer before the exposing layer. From the first CD deviation, a first energy compensation is calculated. Whether the deviation of photoresist sensitivity of two sequential batches is less than 1% is checked. If the deviation of photoresist sensitivity of two sequential batches is less than 1%, a sum of the required exposure energy and the first energy compensation is the exposure energy applied to the exposing layer. Otherwise, a second CD deviation is commutated according to the deviation of photoresist sensitivity of two sequential batches. A second energy compensation is then obtained from the second CD deviation, and a sum of the required exposure energy and the first/second energy compensation is the exposure energy applied to the exposing layer.Type: GrantFiled: August 31, 2001Date of Patent: July 1, 2003Assignee: United MicroelectronicsInventors: Kun-Yuan Chang, Wang-Hsiang Ho, Yu-Ping Huang, Li-Dar Tsai, Chung-Yung Wu
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Patent number: 6566225Abstract: The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide layer is formed thereon. A second polysilicon layer is formed on the oxide layer. The partial second polysilicon layer, the oxide layer, the first polysilicon layer, and the pad oxide layer are removed to expose the partial substrate. The second polysilicon layer and the partial substrate are etched for forming the trench structure in the substrate. An etched depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.Type: GrantFiled: August 6, 2001Date of Patent: May 20, 2003Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Hsin-Huei Chen, Yu-Ping Huang