Patents by Inventor Yu Ru Huang
Yu Ru Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240166874Abstract: A resin composition including a modified maleimide resin is provided. The modified maleimide resin is formed from a dicyclopentadiene (DCPD)-based resin having an amino group and a maleic anhydride by a condensation polymerization. The dicyclopentadiene-based resin having an amino group is formed by nitration reaction and hydrogenation reaction of dicyclopentadiene phenolic resin.Type: ApplicationFiled: April 13, 2023Publication date: May 23, 2024Applicant: NAN YA PLASTICS CORPORATIONInventors: Te-Chao Liao, Yu-Ting Liu, Hung-Yi Chang, Chia-Lin Liu, Wei-Ru Huang
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Publication number: 20240166817Abstract: A resin composition including a modified maleimide resin is provided. The modified maleimide resin is formed from a dicyclopentadiene (DCPD)-based resin having an amino group and a maleic anhydride by a condensation polymerization. The dicyclopentadiene-based resin having an amino group is formed by nitration reaction and hydrogenation reaction of dicyclopentadiene phenolic resin.Type: ApplicationFiled: April 11, 2023Publication date: May 23, 2024Applicant: NAN YA PLASTICS CORPORATIONInventors: Te-Chao Liao, Yu-Ting Liu, Hung-Yi Chang, Chia-Lin Liu, Wei-Ru Huang
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Patent number: 11991880Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.Type: GrantFiled: September 9, 2020Date of Patent: May 21, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Yu Ru Huang, Qian Tao, Yushi Hu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Yongna Li, Lidong Song
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Publication number: 20240161818Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.Type: ApplicationFiled: November 30, 2022Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Li-Ping Huang, Yu-Fang Chen, Chun-Yen Tseng, Tzu-Feng Chang, Chun-Chieh Chang
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Patent number: 11943935Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.Type: GrantFiled: September 26, 2022Date of Patent: March 26, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
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Patent number: 11915755Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.Type: GrantFiled: January 20, 2022Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang, Yu-Fang Chen
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Publication number: 20230150141Abstract: A training data generation device includes a virtual scene generation unit, an orthographic virtual camera, an object-occlusion determination unit, an object-occlusion determination unit and a perspective virtual camera. The virtual scene generation unit is configured for generating a virtual scene, wherein the virtual scene comprises a plurality of objects. The orthographic virtual camera is configured for capturing a vertical projection image of the virtual scene. The object-occlusion determination unit is configured for labeling an occluded-state of each object according to the vertical projection image. The perspective virtual camera is configured for capturing a perspective projection image of the virtual scene. The training data generation unit is configured for generating a training data of the virtual scene according to the perspective projection image and the occluded-state of each object.Type: ApplicationFiled: October 7, 2022Publication date: May 18, 2023Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hung-Chun CHOU, Yu-Ru HUANG, Dong-Chen TSAI
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Publication number: 20230084008Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Publication number: 20230083030Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: November 10, 2022Publication date: March 16, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Publication number: 20220362945Abstract: An object pose estimation system, an execution method thereof and a graphic user interface are provided. The execution method of the object pose estimation system includes the following steps. A feature extraction strategy of a pose estimation unit is determined by a feature extraction strategy neural network model according to a scene point cloud. According to the feature extraction strategy, a model feature is extracted from a 3D model of an object and a scene feature is extracted from the scene point cloud by the pose estimation unit. The model feature is compared with the scene feature by the pose estimation unit to obtain an estimated pose of the object.Type: ApplicationFiled: October 19, 2021Publication date: November 17, 2022Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Dong-Chen TSAI, Ping-Chang SHIH, Yu-Ru HUANG, Hung-Chun CHOU
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Patent number: 11338441Abstract: A calibration system for robot tool including a robot arm adopting a first coordinate system, a tool arranged on a flange of the robot arm, and an imaging device adopting a second coordinate system is disclosed, wherein an image sensing area is established by the image device. A calibration method is also disclosed and includes steps of: controlling the robot arm to move for leading a tool working point (TWP) of the tool enters the image sensing area; recording a current gesture of the robot arm as well as a specific coordinate of the TWP currently in the second coordinate system; obtaining a transformation matrix previously established for describing a relationship between the first and the second coordinate systems; and importing the specific coordinate and the current gesture to the transformation matrix for calculating an absolute position of the TWP in the first coordinate system.Type: GrantFiled: March 5, 2020Date of Patent: May 24, 2022Assignee: DELTA ELECTRONICS, INC.Inventors: Yi-Jiun Shen, Yu-Ru Huang, Hung-Wen Chen
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Patent number: 11145666Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: GrantFiled: May 28, 2020Date of Patent: October 12, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Patent number: 10952361Abstract: A system for detecting electronic components includes a light-source device, a photography device, an adjustment device, and an image-processing device. The light-source device generates a light to illuminate at least one pin of a first electronic component at different rotation angles. The photography device senses the light and generates first and second images corresponding to the pin of the first electronic component at different rotation angles. The adjustment device adjusts the photography device and the light-source device to a first height and a second height, wherein the first images correspond to the first height and the second images correspond to the second height. The image-processing device calculates first feature information of the pin of the first electronic component according the first and second images, and analyzes the state of the pin of the first electronic component according to the first feature information.Type: GrantFiled: August 13, 2019Date of Patent: March 16, 2021Assignee: DELTA ELECTRONICS, INC.Inventors: Yu-Ru Huang, Qi-Ming Huang, Hung-Wen Chen
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Publication number: 20200411547Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.Type: ApplicationFiled: September 9, 2020Publication date: December 31, 2020Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Yu Ru HUANG, Qian TAO, Yushi HU, Jun CHEN, Xiaowang DAI, Jifeng ZHU, Yongna LI, Lidong SONG
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Publication number: 20200337189Abstract: A system for detecting electronic components includes a light-source device, a photography device, an adjustment device, and an image-processing device. The light-source device generates a light to illuminate at least one pin of a first electronic component at different rotation angles. The photography device senses the light and generates first and second images corresponding to the pin of the first electronic component at different rotation angles. The adjustment device adjusts the photography device and the light-source device to a first height and a second height, wherein the first images correspond to the first height and the second images correspond to the second height. The image-processing device calculates first feature information of the pin of the first electronic component according the first and second images, and analyzes the state of the pin of the first electronic component according to the first feature information.Type: ApplicationFiled: August 13, 2019Publication date: October 22, 2020Inventors: Yu-Ru HUANG, Qi-Ming HUANG, Hung-Wen CHEN
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Patent number: 10804287Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.Type: GrantFiled: September 10, 2018Date of Patent: October 13, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Yu Ru Huang, Qian Tao, Yushi Hu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Yongna Li, Lidong Song
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Publication number: 20200295019Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads. where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: May 28, 2020Publication date: September 17, 2020Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Patent number: 10709048Abstract: An electronic-component assembly system is provided in the invention. The electronic-component assembly system includes a gripping device, a light-source device, a photographing device, and an image-processing device. The gripping device grips an electronic component, wherein the electronic component includes at least one pin. The light-source device includes a light source and emits light of the light source. The photographing device senses the light and generates a plurality of first one-dimensional images corresponding to the pins at different rotation angles. The image-processing device is coupled to the photographing device to receive the plurality of first one-dimensional images.Type: GrantFiled: June 5, 2018Date of Patent: July 7, 2020Assignee: DELTA ELECTRONICS, INC.Inventors: Yu-Ru Huang, Hung-Wen Chen
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Publication number: 20200198146Abstract: A calibration system for robot tool including a robot arm adopting a first coordinate system, a tool arranged on a flange of the robot arm, and an imaging device adopting a second coordinate system is disclosed, wherein an image sensing area is established by the image device. A calibration method is also disclosed and includes steps of: controlling the robot arm to move for leading a tool working point (TWP) of the tool enters the image sensing area; recording a current gesture of the robot arm as well as a specific coordinate of the TWP currently in the second coordinate system; obtaining a transformation matrix previously established for describing a relationship between the first and the second coordinate systems; and importing the specific coordinate and the current gesture to the transformation matrix for calculating an absolute position of the TWP in the first coordinate system.Type: ApplicationFiled: March 5, 2020Publication date: June 25, 2020Inventors: Yi-Jiun SHEN, Yu-Ru HUANG, Hung-Wen CHEN
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Patent number: 10680003Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: GrantFiled: September 10, 2018Date of Patent: June 9, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang