Abstract: A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.

Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.

Abstract: A method for a parallelism-aware wavelength-routed optical networks-on-chip design is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing a WRONoC netlist, design specs and design rules; performing a network construction such that potential positions of each core of a plurality of cores, a plurality of waveguides and a plurality of microring resonators (MRRs) are determined to create a topology; performing a message routing to minimize MRR type usage of the MRRs in the topology; and performing a MRR radius selection to select a radius from MRR-radius options for each MRR type in said topology based on a simulated annealing.

Abstract: A method of WDM-aware optical routing for on-chip devices is proposed, which is executed by a computer, the method comprising using the computer to perform the following steps of: performing a path separation to identify signal net candidates; performing a path clustering to find path clusters of the signal net candidates; performing an endpoint placement to find legal locations for WDM endpoints; and performing a pin-to-waveguide routing all nets to corresponding WDM waveguides.

Abstract: An electronic cable collection device includes a holding member and a base seat. At least one magnetic attraction body with magnetism is disposed in the base seat. At least one plane connection face is disposed on a surface of the base seat. The holding member has a holding mouth inward recessed from a periphery of the holding member to form two opposite lateral holding sections, which can be elastically bent. A magnetic attracted body is disposed in each lateral holding section, whereby the magnetic attracted body and a magnetic attraction body can attract each other. The holding mouth can be elastically opened to respectively hold different diameters of electronic cables. By means of the magnetic attraction between the magnetic attracted body and magnetic attraction body, the holding members can be easily, quickly and collectively located on the connection face of the base seat.

Abstract: A computer support frame structure includes two supports each having a bottom section. The bottom sections transversely extend on the same horizontal face. A middle support section is connected with one end of the bottom section. The middle support section obliquely upward extends from the end of the bottom section. A rest section further transversely extends from an upper end of the middle support section in a direction approximately in parallel to the direction of the bottom section. An upper connection member is secured between the middle sections of the middle support sections. A lower connection member is secured between the middle sections of the bottom sections. The upper and lower connection members and the two supports together forma four-bar linkage to enhance the structural stability, whereby a computer can be securely placed on the rest sections.

Abstract: A bicycle cellular phone holder structure includes a base seat having a first end and a second end. The first end is formed with a first threaded hole in which a first rod member is screwed. One end of the first rod member is assembled with a first holding member, while the other end of the first rod member is mated with a rotational member. The rotational member is formed with a second threaded hole in which a second rod member is screwed. The second rod member is assembled with a second holding member. When rotating the first rod member, the first holding member is moved toward the outer side of the first end or the second end and the second holding member is moved toward the outer side of the second end or the first end so that the first and second holding members are synchronously moved.

Abstract: Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements.

Abstract: An engineering change order (ECO) modifying an IC having spare cell instances is implemented by converting active cell instances implementing portions of the IC to be deleted into additional spare cell instances, by creating a technology independent behavioral model of portions of the IC to be added, by selecting spare cell instances to implement the behavior model, and by routing nets to the selected spare cell instances in a way that minimizes a number of metal layers of the IC that are modified.

Abstract: Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements.

Abstract: An engineering change order (ECO) modifying an IC having spare cell instances is implemented by converting active cell instances implementing portions of the IC to be deleted into additional spare cell instances, by creating a technology independent behavioral model of portions of the IC to be added, by selecting spare cell instances to implement the behavior model, and by routing nets to the selected spare cell instances in a way that minimizes a number of metal layers of the IC that are modified.

Abstract: A fin-shaped antenna apparatus for vehicle ratio application is electrically connected to a wireless receiver circuit and receives a radio signal. The fin-shaped antenna apparatus includes a fin-shaped cover, an AM antenna, a signal amplifier circuit board, an FM resonance circuit on the signal amplifier circuit board and a metal base. The AM antenna is separated with the FM resonance circuit. The FM resonance circuit comprises a plurality of inductors to form a resonance circuit and is connected to a metal base for enhancing the signal reception thereof. Therefore the signal quality for vehicle ratio application is enhanced.

Abstract: A fin-shaped antenna apparatus for vehicle ratio application is electrically connected to a wireless receiver circuit and receives a radio signal. The fin-shaped antenna apparatus includes a fin-shaped cover, an AM antenna, a signal amplifier circuit board, an FM resonance circuit on the signal amplifier circuit board and a metal base. The AM antenna is separated with the FM resonance circuit. The FM resonance circuit comprises a plurality of inductors to form a resonance circuit and is connected to a metal base for enhancing the signal reception thereof. Therefore the signal quality for vehicle ratio application is enhanced.

Abstract: A netlist of a schematic diagram is generated. The netlist indicates the connectivity of components through connection lines. A normal display mode is provided in which at least a portion of the components are presented on the display, and connection lines corresponding to the components are also displayed. A topology display mode is provided in which the components are presented on the display without the connection lines. The user can switch between the topology display mode and the normal display mode while editing the schematic diagram. Automatic pin assignment and routing of the connection lines is performed according to the netlist, and is based upon grouping similarly classified connection lines. An abstract display mode is provided that presents abstract lines for a selected component, with a single abstract line running between two connected components. The abstract display mode is combinable with the topology display mode.

Abstract: A netlist of a schematic diagram is generated. The netlist indicates the connectivity of components through connection lines. A normal display mode is provided in which at least a portion of the components are presented on the display, and connection lines corresponding to the components are also displayed. A topology display mode is provided in which the components are presented on the display without the connection lines. The user can switch between the topology display mode and the normal display mode while editing the schematic diagram. Automatic pin assignment and routing of the connection lines is performed according to the netlist, and is based upon grouping similarly classified connection lines. An abstract display mode is provided that presents abstract lines for a selected component, with a single abstract line running between two connected components. The abstract display mode is combinable with the topology display mode.