Abstract: The present invention provides an image processing circuit including a receiving circuit, a reference value calculating circuit, a center luminance value calculating circuit and an output circuit. In the operations of the image processing circuit, the receiving circuit receives image data. The reference value calculating circuit determines a first reference value and a second reference value corresponding to a plurality of pixels of the image data. The center luminance value calculating circuit refers to the first reference value and the second reference value to generate a center luminance value. The output circuit determines output luminance values of the plurality of pixel values according to the image data, the first reference value and the second reference value.

Abstract: A device comprises source/drain regions over a substrate and spaced apart along a first direction, a first gate structure between the source/drain regions, and a first channel structure surrounded by the first gate structure. The first channel structure comprises alternately stacking first semiconductor layers and second semiconductor layers. When viewed in a cross section taken along a second direction perpendicular to the first direction, central axes of the second semiconductor layers are laterally offset from central axes of the first semiconductor layers.

Abstract: A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.

Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.

Abstract: A semiconductor device includes a substrate, a semiconductor strip, an isolation dielectric, a plurality of channel layers, a gate structure, a plurality of source/drain structures, and an isolation layer. The semiconductor strip extends upwardly from the substrate and has a length extending along a first direction. The isolation dielectric laterally surrounds the semiconductor strip. The channel layers extend in the first direction above the semiconductor strip and arrange in a second direction substantially perpendicular to the substrate. The gate structure surrounds each of the channel layers. The source/drain structures are above the semiconductor strip and on either side of the channel layers. The isolation layer is interposed between the semiconductor strip and the gate structure and further interposed between the semiconductor strip and each of the plurality of source/drain structures.

Abstract: An image processing circuit capable of detecting an edge component includes: a selecting circuit acquiring the brightness values of pixels of an image according to the position of a target pixel and a processing region, wherein the pixels include N horizontal lines and M vertical lines; a brightness-variation calculating circuit generating N horizontal-line-brightness-variation values according to brightness variation of the N horizontal lines, and generating M vertical-line-brightness-variation values according to brightness variation of the M vertical lines; a brightness-variation determining circuit choosing a horizontal-line-brightness-variation representative value among the N horizontal-line-brightness-variation values, choosing a vertical-line-brightness-variation representative value among the M vertical-line-brightness-variation values, and choosing a brightness-variation representative value between the two representative values; an energy-variation calculating circuit generating an energy-variation

Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.

Abstract: A device comprises source/drain regions over a substrate and spaced apart along a first direction, a first gate structure between the source/drain regions, and a first channel structure surrounded by the first gate structure. The first channel structure comprises alternately stacking first semiconductor layers and second semiconductor layers. When viewed in a cross section taken along a second direction perpendicular to the first direction, central axes of the second semiconductor layers are laterally offset from central axes of the first semiconductor layers.

Abstract: The present invention provides an image processing circuit and associated image processing method. In the image processing circuit, a characteristic value calculation circuit is designed to calculate the plurality of characteristic values of consecutive-three-pixels with increasing/decreasing brightness, the plurality of left-side characteristic values of consecutive-three-pixels with increasing/decreasing brightness and the plurality of right-side characteristic values of consecutive-three-pixels with increasing/decreasing brightness, for the brightness adjustments. The adjusted brightness values of the present invention have sharper edges to improve the image quality.

Abstract: The present invention discloses an image processing circuit, wherein the image processing circuit comprises a receiving circuit, a sharpness processing circuit, a luminance variation processing circuit and an output circuit. In the operations of the image processing circuit, the receiving circuit is configured to receive image data; the sharpness processing circuit is configured to perform a high-pass filtering operation on the image data to generate processed image data; the luminance variation processing is configured to determine a high frequency component of each pixel within the image data, and for each pixel, the luminance variation processing circuit is configured to calculate a difference between high frequency components of the pixel and neighboring pixel(s) to generate auxiliary image data; and the output circuit is configured to generate output image according to the processed image data and the auxiliary image data.

Abstract: An ultrasonic cutter includes a tool holder and an ultrasonic oscillator. The tool holder has a lower circular air-out aisle defined by sleeving an inner ring and an outer ring. The inner ring has oppositely a first surface and a second surface, and the outer ring has oppositely a third surface and a fourth surface. A gap spacing the first surface from the third surface has an upper air inlet and a lower air outlet. The second surface has a lower inner inclined surface forming a first angle with the first surface. The fourth surface has an outer inclined surface forming a second angle with the third surface. The ultrasonic oscillator, disposed in a chamber of the tool holder spatially connected with the gap, is used for providing ultrasonic oscillation to a cutter. In addition, a cooling and chip diversion system for the ultrasonic cutter is also provided.

Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.

Abstract: The present disclosure generally relates to a gate-all-around (GAA) transistor. The GAA transistor may include regrown source/drain layers in source/drain stressors. Atomic ratio differences among the regrown source/drain layers are tuned to reduce strain mismatch among the semiconductor nanosheets. Alternatively, the GAA transistor may include strained channels formed using a layer stack of alternating semiconductor layers having different lattice constants.

Abstract: A method includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate; forming a dummy gate structure across the fin structure; etching portions of the fin structure to expose portions of the substrate; forming source/drain stressors over the exposed portions of the substrate; after forming the source/drain stressors, removing the dummy gate structure; after removing the dummy gate structure, removing the first semiconductor layers such that the second semiconductor layers are suspended between the source/drain stressors; and forming a gate structure to surround each of the suspended second semiconductor layers. The source/drain stressors each comprise a first source/drain layer and a second source/drain layer over the first source/drain layer. An atomic concentration of a Group IV element or a Group V element in the second source/drain layer is greater than that in the first source/drain layer.

Abstract: A pipe enlarging device includes a base, an operation unit and a clamping unit. The clamping unit is received in the base, and includes movable front and rear clamps and a front threaded rod. The front and rear clamps are resiliently movable when the front threaded rod is rotated so as to form an adjustable clamping area between the front and rear clamps. The clamping area is used to clamp pipes of different sizes. The operation unit includes a top threaded rod with a cone-shaped member which is used to enlarge the inner diameter of the pipes.

Abstract: A pipe enlarging device includes a base, an operation unit and a clamping unit. The clamping unit is received in the base and includes movable front, rear, left and right clamps, multiple resilient members and a front threaded rod. The front, rear, left and right clamps are resiliently movable when the front threaded rod is rotated so as to form an adjustable clamping area between the front, rear, left and right clamps. The clamping area is used to clamp pipes of different sizes. The operation unit includes a top threaded rod with a cone-shaped member which is used to enlarge the inner diameter of the pipes.

Abstract: The present invention provides an image processing circuit, wherein the image processing circuit comprises a receiving circuit, an image dividing circuit, a first image enlargement circuit, a second image enlargement circuit and an output circuit. In the operations of the image processing circuit, the receiving circuit receives image data, the image dividing circuit divides a pixel value of each pixel of the image data into two parts to generate first image data and second image data, the first image enlargement circuit enlarges the first image data in a linear manner to generate enlarged first image data, the second image enlargement circuit enlarges the second image data in a non-linear manner to generate enlarged second image data, and the output circuit generates an output image according to the enlarged first image data and the enlarged second image data.

Abstract: A power and signal transmission device for a spindle of a machine tool is provided. The power and signal transmission device includes a spindle fixing portion, a shaft rotating portion, a power transmission component and a signal transmission component. The spindle fixing portion is provided with a power input end, a primary side power induction coil, a secondary side signal induction coil and at least one signal output end. The shaft rotating portion is provided with a joining end surface for bonding to a holder, a secondary side power induction coil and a primary side signal induction coil, and is rotatable with respect to the spindle fixing portion. The power transmission component transmits an electrical energy from the power input end. The signal transmission component transmits a holder signal to the signal output end. Each of the power and signal transmission components includes at least one elastic pogo pin.

Abstract: A power and signal transmission device for a spindle of a machine tool is provided. The power and signal transmission device includes a spindle fixing portion, a shaft rotating portion, a power transmission component and a signal transmission component. The spindle fixing portion is provided with a power input end, a primary side power induction coil, a secondary side signal induction coil and at least one signal output end. The shaft rotating portion is provided with a joining end surface for bonding to a holder, a secondary side power induction coil and a primary side signal induction coil, and is rotatable with respect to the spindle fixing portion. The power transmission component transmits an electrical energy from the power input end. The signal transmission component transmits a holder signal to the signal output end. Each of the power and signal transmission components includes at least one elastic pogo pin.

Abstract: An image processing circuit capable of detecting an edge component includes: a selecting circuit acquiring the brightness values of pixels of an image according to the position of a target pixel and a processing region, wherein the pixels include N horizontal lines and M vertical lines; a brightness-variation calculating circuit generating N horizontal-line-brightness-variation values according to brightness variation of the N horizontal lines, and generating M vertical-line-brightness-variation values according to brightness variation of the M vertical lines; a brightness-variation determining circuit choosing a horizontal-line-brightness-variation representative value among the N horizontal-line-brightness-variation values, choosing a vertical-line-brightness-variation representative value among the M vertical-line-brightness-variation values, and choosing a brightness-variation representative value between the two representative values; an energy-variation calculating circuit generating an energy-variation