Abstract: Disclosed herein are drug-containing vesicles, each of which includes a carbon dot liposome (C-dot liposome) formed by a plurality of Janus particles, which are self-assembled into the C-dot liposome; and a drug encapsulated within the C-dot liposome. Also disclosed herein is a method of producing the drug-containing vesicles. The method includes, mixing a plurality of Janus particles with a drug solution (e.g., an anti-cancer drug solution) to form a mixed solution; and producing the drug-containing vesicles either by a film-hydration method or an injection method. In the film-hydration method, the mixed solution is condensed until a film-like structure is formed; and sonicating the film-like structure in a salt solution to produce the drug-containing vesicle. In the injection method, the mixed solution is rapidly injected into a salt solution to produce the drug-containing vesicle. Also encompasses in the present disclosure are methods for treating a subject afflicted with a cancer.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: A detection kit is suitable for detecting a target compound. The detection kit includes a reaction container, an inspection solution composed of a hydrophobic solvent, and a plurality of fluorescent materials. The inspection solution is disposed in the reaction container. The fluorescent materials are dispersed in the inspection solution. The fluorescent material emits fluorescence, and after the fluorescent materials interact with the target compound, the intensity of the fluorescence emitted by the fluorescent materials is reduced.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.

Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

Abstract: A sensing paper suitable for sensing a target substance is provided. The sensing paper includes a filter paper, a wax, and a plurality of fluorescent materials. The wax is printed on the filter paper, wherein the sensing paper has a plurality of opening patterns, and each of the opening patterns respectively exposes a portion of the filter paper. The plurality of fluorescent materials is attached to the portion of the filter paper that is exposed by each of the opening patterns. Each of the fluorescent materials emits fluorescence, and after the fluorescent materials react with the target substance, an intensity of the fluorescence emitted by the fluorescent materials is quenched.

Abstract: A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.

Abstract: A server device including a chassis having an accommodating space and an opening, a least one server having a front part and a back part, and at least one connecting rod assembly having a first connecting rod, a second connecting rod, and a third connecting rod. The server may be located in the accommodating space and be drawable from the opening. The first connecting rod is pivoted on the front part of the server. The second connecting rod is pivoted on the back part of the at least one server. An end of the third connecting rod is pivoted on the first connecting rod, and another end of the third connecting rod is pivoted on the second connecting rod. The first connecting rod is rotatable relative to the server to move the third connecting rod, so that the second connecting rod is fastened to the chassis.

Abstract: A server device including a chassis having an accommodating space and an opening, a least one server having a front part and a back part, and at least one connecting rod assembly having a first connecting rod, a second connecting rod, and a third connecting rod. The server may be located in the accommodating space and be drawable from the opening. The first connecting rod is pivoted on the front part of the server. The second connecting rod is pivoted on the back part of the at least one server. An end of the third connecting rod is pivoted on the first connecting rod, and another end of the third connecting rod is pivoted on the second connecting rod. The first connecting rod is rotatable relative to the server to move the third connecting rod, so that the second connecting rod is fastened to the chassis.

Abstract: The present disclosure relates to an electrostatic discharge (ESD) protection circuit integrated with a gallium nitride (GaN) based transistor and configured to clamp a gate input voltage of the gallium nitride (GaN) based transistor during an ESD surge event, and associated methods. In some embodiments, the ESD protection circuit includes a first ESD protection stage and a second ESD protection stage connected between a gate terminal and a source terminal of the GaN based transistor. The first ESD protection stage includes a first plurality of GaN based gate-to-source shorted transistors connected in series and further connected to a first terminal of a first resistor. The second ESD protection stage is connected to the first ESD protection stage in parallel. The second ESD protection stage comprises a first GaN based shunt transistor having a gate terminal connected to the first terminal of the first resistor.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A layer of gate isolation material is located over the layer of doped III-N semiconductor material. A gate structure is disposed over layer of gate isolation material, such that the gate structure is separated from the electron supply layer by the layer of gate isolation material and the layer of doped III-N semiconductor material. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the layer of gate isolation material provides a barrier that gives the rectifier device a low leakage.

Abstract: Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.

Abstract: A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: Some embodiments relate to a method of dicing a semiconductor wafer. The semiconductor wafer that includes a device structure that is formed within a device layer. The device layer is arranged within an upper surface the device layer. A crack stop is formed, which surrounds the device structure and reinforces the semiconductor wafer to prevent cracking during dicing. A laser is used to form a groove along a scribe line outside the crack stop. The groove extends completely through the device layer, and into an upper surface region of the semiconductor wafer. The semiconductor wafer is then cut along the grooved scribe line with a cutting blade to singulate the semiconductor wafer into two or more die. By extending the groove completely through the device layer, the method avoids damage to the device layer caused by the blade saw, and thus avoids an associated performance degradation of the device structure.