Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

Abstract: A semiconductor device includes a first transistor and a protection structure. The first transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, and a channel layer disposed on the gate dielectric. The protection structure is laterally surrounding the gate electrode, the gate dielectric and the channel layer of the first transistor. The protection structure includes a first capping layer and a dielectric portion. The first capping layer is laterally surrounding and contacting the gate electrode, the gate dielectric and the channel layer of the first transistor. The dielectric portion is disposed on the first capping layer and laterally surrounding the first transistor.

Abstract: The present disclosure provides a thin-film-deposition equipment with shielding device, which includes a reaction chamber, a carrier and a shielding device, wherein a portion of the shielding device and the carrier are disposed within the reaction chamber. The shielding device includes a first-shield member, a second-shield member and a driver. The driver interconnects the first-shield member and the second-shield member, for driving the first-shield member and the second-shield member to move in opposite directions. During a deposition process, the driver swings the shield members away from each other into an open state. During a cleaning process, the driver swings the shield members toward each other into a shielding state for covering the carrier, such that to prevent polluting the carrier during the process of cleaning the thin-film-deposition equipment.

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.

Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

Abstract: Provided is a semiconductor device includes a gate electrode, a gate dielectric layer, a channel layer, an insulating layer, a first source/drain electrode and a second source/drain electrode, a second dielectric layer, and a stop segment. The gate electrode is located within a first dielectric layer that overlies a substrate. The gate dielectric layer is located over the gate electrode. The channel layer is located on the gate dielectric layer. The insulating layer is located over the channel layer. The first source/drain electrode and the second source/drain electrode are located in the insulating layer, and connected to the channel layer. The second dielectric layer is beside one of the first source/drain electrode and the second source/drain electrode. The stop segment is embedded in the second dielectric layer.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: A memory device includes a multi-layer stack, a channel layer, a memory material layer and at least three conductive pillars. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer and memory material layer penetrate through the plurality of conductive layers and the plurality of dielectric layers. The at least three conductive pillars are surrounded by the channel layer and the memory material layer, wherein the at least three conductive pillars are electrically connected to conductive layers respectively. The at least three conductive pillars includes a first, a second and a third conductive pillars disposed between the first conductive pillar and the second conductive pillar. A third width of the third conductive pillar is smaller than a first width of the first conductive pillar and a second width of the second conductive pillar.

Abstract: The invention provides a deposition equipment with a shielding mechanism, which includes a reaction chamber, a carrier, a cover ring and a shielding mechanism. The shielding mechanism includes a first bearing arm, a second bearing arm, a first shielding plate and a second shielding plate. The first and second shielding plates are respectively placed on the first and second bearing arms. There are corresponding alignment units between the lower surface of the first and second shielding plates and the upper surface the carrier, so that the first and second shielding plates can be aligned with the carrier. There is also a corresponding alignment unit between the upper surface of the first and second shielding plates and the lower surface the cover ring, so that the cover ring can be aligned with the first and second shielding plates to define a cleaning space in the reaction chamber.

Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.

Abstract: A resin composition includes 50 parts by weight of a vinyl-containing polyphenylene ether resin, 1 part by weight to 30 parts by weight of a styrene-butadiene-styrene block copolymer and 0.5 part by weight to 30 parts by weight of a zinc molybdate-covered silica, wherein the zinc molybdate-covered silica has a mass ratio of zinc molybdate to silica of between 1:9 and 2:8. The resin composition may be used to make various articles, such as a prepreg, a resin film, a laminate or a printed circuit board, and at least one of the following properties can be improved, including gel time stability, copper foil peeling strength, difference rate of dissipation factor and conductive anodic filament test.

Abstract: A resin composition includes 50 parts by weight of a vinyl-containing polyphenylene ether resin, 1 part by weight to 30 parts by weight of a styrene-butadiene-styrene block copolymer and 0.5 part by weight to 30 parts by weight of a zinc molybdate-covered silica, wherein the zinc molybdate-covered silica has a mass ratio of zinc molybdate to silica of between 1:9 and 2:8. The resin composition may be used to make various articles, such as a prepreg, a resin film, a laminate or a printed circuit board, and at least one of the following properties can be improved, including gel time stability, copper foil peeling strength, difference rate of dissipation factor and conductive anodic filament test.

Abstract: A multi-band network node has selectable backhaul/fronthaul configurations. Network nodes provide multi-band operation to take advantage of higher Internet speeds and to support lower latency (> 2 Gbps, < 4 ms latency) applications. A greater Wi-Fi device count (capacity) is supported by implementing communication over additional bands. Increased bandwidth is made available between connected nodes by selectively combining backhaul throughputs. Hardware quality-of-service (QoS) is provided by splitting traffic flows for low latency and data applications. Network coverage is extended by dynamic assignment of backhaul connections and by configuring unused backhauls as fronthauls.

Abstract: Disclosed are an epoxy resin composition and an article made therefrom, the epoxy resin composition comprising an epoxy resin and a co-hardener, wherein: relative to the epoxy resin having a total equivalent of epoxy group of 1, the co-hardener comprises: (A) an acid anhydride having a total equivalent of acid anhydride group of 0.044-0.183; (B) a polyester having a total equivalent of ester group of 0.120-0.550; (C) a first phenolic resin having an equivalent of hydroxyl group of 0.092-0.550; and (D) a second phenolic resin having an equivalent of hydroxyl group of 0.143-0.592; and a sum of equivalent of functional groups of the co-hardener is 0.84-1.11.

Abstract: The present invention provides a miniature gas sensor, which comprises a gas sensor chip. The gas sensor chip includes a hollow structure on the back. An insulating layer is disposed below the sensing material. A miniature heating device is disposed surrounding the sensing material. The sensing material is adhered to the sensing electrodes. The sensing material includes two metal oxide semiconductors or a compound structure of the sensing layer having a metal oxide semiconductor and a reaction layer with a rough surface. An interface layer is sandwiched between the two metal oxide layers for increasing the efficiency in sensing gas. The gas sensor according to the present invention can be implemented on silicon substrate with hollow structures. In addition, the size of the chip can be miniaturized.

Abstract: A light-emitting housing is disclosed. The light-emitting housing includes a light-emitting module and a housing. The light-emitting module includes a light guide plate and at least one light-emitting unit. The light guide plate includes an upper surface, a lower surface, and a plurality of dot regions, the dot regions are located on the lower surface, and the at least one light-emitting unit provides a plurality of light beams incident to the light guide plate. The housing is disposed above the light-emitting module and located on the upper surface of the light guide plate, and the housing includes at least one transparent region. Some of the light beams emitted by the at least one light-emitting unit are reflected through the dot regions and penetrate the upper surface of the light guide plate and the at least one transparent region.

Abstract: The present invention provides a gas sensor structure comprising a gas sensing chip. The back of the sensing material is a hollow structure. An insulating layer is below the sensing material. A micro heating is disposed surrounding the sensing material. The sensing material adheres to sensing electrodes. The sensing material is a complex structure including a metal oxide semiconductor and a roughened lanthanum-carbonate gas sensing layer. The thickness of the metal oxide semiconductor is between 0.2 ?m and 10 ?m; the thickness of the roughened lanthanum-carbonate gas sensing layer is between 0.1 ?m and 4 ?m; and the size of the back etching holes is smaller than 1*1 mm. By using the gas sensor structure according to the present invention, a suspended gas sensing structure can be fabricated on a silicon substrate and the chip size can be minimized.