Patents by Inventor Yu-Ting Cheng
Yu-Ting Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130120903Abstract: A decoupling device including a lead frame, multiple capacitor units, a protective layer and a packaging element is provided. The lead frame includes a cathode terminal portion and at least two opposite anode terminal portions disposed at two ends of the cathode terminal portion. The two anode terminal portions are electrically connected with each other through a conductive line. The capacitor units are connected in parallel and disposed on the lead frame. Each capacitor unit has a cathode portion and an opposite anode portion. The cathode portion is electrically connected with the cathode terminal portion. The anode portion is electrically connected with the anode terminal portion. The protective layer wraps at least one of the anode portion and the cathode portion of the capacitor unit. The packaging element covers the lead frame, the capacitor units and the protective layer. The packaging element exposes a bottom surface of the lead frame.Type: ApplicationFiled: January 15, 2012Publication date: May 16, 2013Applicant: Industrial Technology Research InstituteInventors: Yi-Hsiu Pan, Yu-Ting Cheng, Li-Duan Tsai, Chi-Lun Chen, Cheng-Liang Cheng
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Patent number: 8373250Abstract: The present invention relates to a an on-chip inductor structure and a method for manufacturing the same. The an on-chip inductor structure according to the present invention comprises a substrate, a porous layer, a plurality of conductors, and an inductor. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of conductors is disposed in the plurality of voids, respectively; and the inductor is disposed on the porous layer. Because the plurality of conductors is used as the core of the inductor, the inductance is increased effectively and the area of the an on-chip inductor is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered.Type: GrantFiled: October 28, 2009Date of Patent: February 12, 2013Assignee: National Chiao Tung UniversityInventors: Tzu-Yuan Chao, Ming-Chieh Hsu, Yu-Ting Cheng, Chih Chen, Chien-Min Lin
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Publication number: 20130023706Abstract: This invention relates to compositions comprising fluid hydrocarbon products, and to methods for making fluid hydrocarbon products via catalytic pyrolysis. Some embodiments relate to methods for the production of specific aromatic products (e.g., benzene, toluene, naphthalene, xylene, etc.) via catalytic pyrolysis. Some such methods involve the use of a composition comprising a mixture of a solid hydrocarbonaceous material and a heterogeneous pyrolytic catalyst component. The methods described herein may also involve the use of specialized catalysts. For example, in some cases, zeolite catalysts may be used.Type: ApplicationFiled: August 30, 2012Publication date: January 24, 2013Applicant: University of MassachusettsInventors: George W. Huber, Yu-Ting Cheng, Torren Carlson, Tushar Vispute, Jungho Jae, Geoff Tompsett
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Publication number: 20120323539Abstract: A method and a non-transitory computer readable medium thereof for thermal analysis modeling are provided. The method includes establishing an electrothermal network ? model on the basis of electronic modules of an electronic system to define a heat source, propagation paths and a common base of the electronic system. Observation points in the electronic system are defined, in which each observation point is located at an isothermal surface enclosing a volume surrounding a reference point, and where the reference point is the heat source or one observation point. A heat conduction temperature difference and a heat convection temperature difference are calculated according to a power density function, a thermal conductivity coefficient and a distance vector between the reference point and each observation point. A temperature distribution is established according to the heat conduction and the heat convection temperature difference and a defined temperature of the common base.Type: ApplicationFiled: August 8, 2011Publication date: December 20, 2012Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Chien-Chang Chen, Yu-Ting Cheng
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Patent number: 8277643Abstract: This invention relates to compositions and methods for fluid hydrocarbon product, and more specifically, to compositions and methods for fluid hydrocarbon product via catalytic pyrolysis. Some embodiments relate to methods for the production of specific aromatic products (e.g., benzene, toluene, naphthalene, xylene, etc.) via catalytic pyrolysis. Some such methods may involve the use of a composition comprising a mixture of a solid hydrocarbonaceous material and a heterogeneous pyrolytic catalyst component. In some embodiments, the mixture may be pyrolyzed at high temperatures (e.g., between 500° C. and 1000° C.). The pyrolysis may be conducted for an amount of time at least partially sufficient for production of discrete, identifiable biofuel compounds. Some embodiments involve heating the mixture of catalyst and hydrocarbonaceous material at high rates (e.g., from about 50° C. per second to about 1000° C. per second). The methods described herein may also involve the use of specialized catalysts.Type: GrantFiled: March 3, 2009Date of Patent: October 2, 2012Assignee: University of MassachusettsInventors: George W. Huber, Yu-Ting Cheng, Torren Carlson, Tushar Vispute, Jungho Jae, Geoff Tompsett
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Publication number: 20120235275Abstract: The present invention relates to an on-chip electronic device and a method for manufacturing the same. The on-chip electronic device according to the present invention comprises a substrate, a porous layer, a plurality of magnetic bodies, and an electronic member layer. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of magnetic bodies is disposed in the plurality of voids, respectively; and the electronic member layer is disposed on one side of the porous layer, such as upper side of or lower sider of the porous layer. Because the plurality of magnetic bodies is used as the core of the inductance, the inductance is increased effectively and the area of the on-chip electronic device is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered.Type: ApplicationFiled: May 31, 2012Publication date: September 20, 2012Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: YU-TING CHENG, TZU-YUAN CHAO, KUAN-MING CHEN, HSIN-FU HSU
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Publication number: 20120203042Abstract: This invention relates to compositions and methods for fluid hydrocarbon product, and more specifically, to compositions and methods for fluid hydrocarbon product via catalytic pyrolysis. Some embodiments relate to methods for the production of specific aromatic products (e.g., benzene, toluene, naphthalene, xylene, etc.) via catalytic pyrolysis. Some such methods may involve the use of a composition comprising a mixture of a solid hydrocarbonaceous material and a heterogeneous pyrolytic catalyst component. In some embodiments, an olefin compound may be co-fed to the reactor and/or separated from a product stream and recycled to the reactor to improve yield and/or selectivity of certain products. The methods described herein may also involve the use of specialized catalysts. For example, in some cases, zeolite catalysts may be used. In some instances, the catalysts are characterized by particle sizes in certain identified ranges that can lead to improve yield and/or selectivity of certain products.Type: ApplicationFiled: September 9, 2010Publication date: August 9, 2012Applicants: ANELLOTECH, INC., UNIVERSITY OF MASSACHUSETTSInventors: George W. Huber, Anne Mae Gaffney, Jungho Jae, Yu-Ting Cheng
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Publication number: 20120162852Abstract: A decoupling device including a lead frame and at least one capacitor unit assembly is provided. The lead frame includes a cathode terminal portion and at least two opposite anode terminal portions located at two ends of the cathode terminal portion. The two anode terminal portions are electrically connected with each other through a conductive line. The capacitor unit assembly includes multiple capacitor elements. The multiple capacitor elements of the capacitor unit assembly is connected in parallel, arrayed on the same plane and disposed on the lead frame. Each capacitor element has a cathode portion and an anode portion opposite to each other. The cathode portion of the capacitor element is electrically connected with the cathode terminal portion. The anode portion of the capacitor element is electrically connected with the anode terminal portion. When multiple capacitor unit assemblies exists, the capacitor unit assemblies are arrayed in a stacked way.Type: ApplicationFiled: March 21, 2011Publication date: June 28, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Cheng-Liang Cheng, Yi-Hsiu Pan, Yu-Ting Cheng, Li-Duan Tsai
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Publication number: 20120086433Abstract: The invention discloses an MEMS-based current sensing apparatus including: a flexible substrate joined onto an conducting wire; a sensing unit formed of an MEMS structure and disposed on the flexible substrate, the sensing unit outputting a response to a electromagnetic field induced by a current flowing in the conducting wire; and a readout circuit disposed on the flexible substrate and coupled to the sensing unit, the readout circuit monitoring the response to the electromagnetic field and calculating the amount of the current flow.Type: ApplicationFiled: December 28, 2010Publication date: April 12, 2012Applicant: Industrial Technology Research InstituteInventors: SHIH-HSIEN CHENG, WU-CHI HO, CHENG-TING LIN, YU-TING CHENG, PEI-FANG LIANG, YUNG-CHANG CHEN
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Publication number: 20120032320Abstract: A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is used to remove the sacrificial layer underneath the flexible substrate. The instant disclosure applies standardized micro-fabrication process for integrating chip(s) onto the flexible substrate. Without using special materials or fabrication procedures, the instant disclosure offers a cost-effective fabrication method for flexible micro-systems.Type: ApplicationFiled: October 7, 2010Publication date: February 9, 2012Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: TZU-YUAN CHAO, CHIA-WEI LIANG, YU-TING CHENG
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Publication number: 20110136662Abstract: A catalytic seeding control method is disclosed. A catalytic metal film is deposited on a substrate with a nonwettable inclined surface. The catalytic metal film is then melted to form metal droplets. The metal droplets roll along the nonwettable inclined surface and aggregate to form a singular catalytic seed on the bottom of the nonwettable inclined surface. Then, the location of the singular catalytic seed is precisely controlled. Also, the size of the catalytic seed is controlled by adjusting the size of the inclined surface and the thickness of the catalytic metal layer to grow a one-dimensional structure with specific localization and single well-aligned manipulated size. The structure is utilized for the integrated microelectronic device fabrication.Type: ApplicationFiled: March 11, 2010Publication date: June 9, 2011Inventors: C.C. Chen, Yu-Ting Cheng, Lun-Hao Hsu, Kai Rern
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Publication number: 20110042782Abstract: The present invention relates to a an on-chip inductor structure and a method for manufacturing the same. The an on-chip inductor structure according to the present invention comprises a substrate, a porous layer, a plurality of conductors, and an inductor. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of conductors is disposed in the plurality of voids, respectively; and the inductor is disposed on the porous layer. Because the plurality of conductors is used as the core of the inductor, the inductance is increased effectively and the area of the an on-chip inductor is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered.Type: ApplicationFiled: October 28, 2009Publication date: February 24, 2011Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: TZU-YUAN CHAO, MING-CHIEH HSU, YU-TING CHENG, CHIH CHEN, CHIEN-MIN LIU
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Patent number: 7880305Abstract: The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface.Type: GrantFiled: November 7, 2002Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Yu-Ting Cheng, Sherif A. Goma, John Harold Magerlein, Sampath Purushothaman, Carlos Juan Sambucetti, George Frederick Walker
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Patent number: 7870378Abstract: A boot up method makes an electronic system boot up by a processor according to a boot code in a NAND flash memory and includes the following steps. First, the flash memory storing a boot code or boot codes is provided. Next, a first boot code is copied to an XIP memory in response to a hardware reset signal. Then, the processor executes the first boot code in the XIP memory and thus makes the system boot up. Next, whether the system boots up successfully is judged after a time delay. When the system fails to boot up, the system is reset and a second boot code is copied to the XIP memory. Thereafter, the processor executes the second boot code in the XIP memory and thus boots up the system. If the system still fails to boot up, the above-mentioned steps are repeated until the system boots up successfully.Type: GrantFiled: October 3, 2007Date of Patent: January 11, 2011Assignee: Magic Pixel Inc.Inventors: Yu-Hao Kuo, Chi-Houn Ma, Yu-Ting Cheng, Chun-Chieh Huang, Hua-Lin Chang
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Publication number: 20090302454Abstract: The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface.Type: ApplicationFiled: August 11, 2009Publication date: December 10, 2009Inventors: Yu- Ting Cheng, Sherif A. Goma, John Harold Magerlein, Sampath Purushothaman, Carlos Juan Sambucetti, George Frederick Walker
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Publication number: 20090227823Abstract: This invention relates to compositions and methods for fluid hydrocarbon product, and more specifically, to compositions and methods for fluid hydrocarbon product via catalytic pyrolysis. Some embodiments relate to methods for the production of specific aromatic products (e.g., benzene, toluene, naphthalene, xylene, etc.) via catalytic pyrolysis. Some such methods may involve the use of a composition comprising a mixture of a solid hydrocarbonaceous material and a heterogeneous pyrolytic catalyst component. In some embodiments, the mixture may be pyrolyzed at high temperatures (e.g., between 500° C. and 1000° C.). The pyrolysis may be conducted for an amount of time at least partially sufficient for production of discrete, identifiable biofuel compounds. Some embodiments involve heating the mixture of catalyst and hydrocarbonaceous material at high rates (e.g., from about 50° C. per second to about 1000° C. per second). The methods described herein may also involve the use of specialized catalysts.Type: ApplicationFiled: March 3, 2009Publication date: September 10, 2009Applicant: University of MassachusettsInventors: George W. Huber, Yu-Ting Cheng, Torren Carlson, Tushar Vispute, Jungho Jae, Geoff Tompsett
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Patent number: 7451415Abstract: In this invention, a closed-form integral model for on-chip suspended rectangular spiral inductor is presented. The model of this invention bases on the Kramers-Kronig relations, field theory, and solid state physics to characterize a spiral inductor which RFIC designers could easily have the optimal design utilizing this analytical method. Meanwhile, this model can provide satisfactory prediction to the inductance and self-resonant frequency of the spiral inductor without complicated geometry analysis. Furthermore, unlike conventional formulations only based on circuit parameters, this model could safely predict the inductance and the self-resonant frequency when altering the material (excluding ferromagnetic materials) of a spiral inductor.Type: GrantFiled: May 18, 2006Date of Patent: November 11, 2008Assignee: National Chiao Tung UniversityInventors: Chien-Chang Chen, Yu-Ting Cheng
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Publication number: 20080082814Abstract: A boot up method makes an electronic system boot up by a processor according to a boot code in a NAND flash memory and includes the following steps. First, the flash memory storing a boot code or boot codes is provided. Next, a first boot code is copied to an XIP memory in response to a hardware reset signal. Then, the processor executes the first boot code in the XIP memory and thus makes the system boot up. Next, whether the system boots up successfully is judged after a time delay. When the system fails to boot up, the system is reset and a second boot code is copied to the XIP memory. Thereafter, the processor executes the second boot code in the XIP memory and thus boots up the system. If the system still fails to boot up, the above-mentioned steps are repeated until the system boots up successfully.Type: ApplicationFiled: October 3, 2007Publication date: April 3, 2008Applicant: Magic Pixel Inc.Inventors: Yu-Hao Kuo, Chi-Houn Ma, Yu-Ting Cheng, Chun-Chieh Huang, Hua-Lin Chang
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Publication number: 20080008900Abstract: A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.Type: ApplicationFiled: September 24, 2007Publication date: January 10, 2008Inventors: Yu-Ting Cheng, Stefanie Chiras, Donald Henderson, Sung-Kwon Kang, Stephen Kilpatrick, Henry Nye, Carlos Sambucetti, Da-Yuan Shih
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Patent number: 7273803Abstract: A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.Type: GrantFiled: December 1, 2003Date of Patent: September 25, 2007Assignee: International Business Machines CorporationInventors: Yu-Ting Cheng, Stefanie Ruth Chiras, Donald W. Henderson, Sung-Kwon Kang, Stephen James Kilpatrick, Henry A. Nye, III, Carlos J. Sambucetti, Da-Yuan Shih