Patents by Inventor Yu Tsai

Yu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240179699
    Abstract: The present invention provides a control method of an electronic device, wherein the control method includes the steps of: using a first beacon setting to transmit beacons; if a wireless communication state of the electronic device satisfies a condition, using a second beacon setting to transmit beacons; wherein the first beacon setting and the second beacon setting have different beacon periods or different payload sizes.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Applicant: MEDIATEK INC.
    Inventors: Ming-Yen Tsai, Tsung-Hsuan Wu, Ching-Yu Kuo
  • Publication number: 20240175295
    Abstract: An electronic door lock and a method for automatically judging a locking/unlocking direction of the electronic door lock are provided. The electronic door lock includes a latch assembly, a lock body, a transmission rod, a locking detection module, a motor module and a motion detection circuit board. The transmission rod is connected with the latch assembly for controlling the latch assembly. The motion detection circuit board is electrically connected with the motor module and the locking detection module. The motion detection circuit board controls the motor module to drive the transmission rod. Consequently, a latch bolt of the latch assembly is protruded out in a first direction or a second direction. By detecting the status of the transmission rod, the locking detection module judges whether the latch bolt is protruded to a locking position.
    Type: Application
    Filed: January 4, 2023
    Publication date: May 30, 2024
    Inventors: Kuan-Po Huang, Wen-Hann Tsai, Tung-Yu Lai
  • Publication number: 20240176093
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
  • Patent number: 11996293
    Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin protruding from the substrate, an isolation feature disposed on the substrate and on sidewalls of the first and second semiconductor fins, a gate structure disposed on the isolation feature. The semiconductor device also includes a dielectric fin disposed on the isolation feature and sandwiched between the first and second semiconductor fins. A middle portion of the dielectric fin separates the gate structure into a first gate structure segment engaging the first semiconductor fin and a second gate structure segment engaging the second semiconductor fin.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20240170381
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan CAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20240170603
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface, an optical device disposed on the first surface of the substrate, and an electronic device disposed on the second surface of the substrate. A power of the electronic device is greater than a power of the optical device. A vertical projection of the optical device on the first surface is spaced apart from a vertical projection of the electronic device on the second surface by a distance greater than zero.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Yi WU, Chang Chin TSAI, Bo-Yu HUANG, Ying-Chung CHEN
  • Publication number: 20240168254
    Abstract: An imaging lens assembly includes a lens barrel, optical lens elements, an annular retaining element and a nano-microstructure. The optical lens elements include at least one optical lens element disposed in the lens barrel. The annular retaining element is physically contacted with the optical lens element, and the annular retaining element includes an object-side surface, an image-side surface, an outer diameter surface and a light-through hole. The outer diameter surface is connected to the object-side surface and the image-side surface. The light-through hole is formed by gradually tapering from the object-side surface and the image-side surface towards the optical axis. The nano-microstructure has a plurality of irregular ridged convexes. The nano-microstructure is located between a lens barrel area defined via the lens barrel and a lens element area defined via the optical lens element on a direction vertical to the optical axis.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 23, 2024
    Inventors: Ssu-Hsin LIU, Heng-Yi SU, Liang-Chieh WENG, Wen-Yu TSAI, Ming-Ta CHOU
  • Publication number: 20240168985
    Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a first performance metric score may be determined based upon first content item text. A plurality of similarity scores associated with a plurality of sets of content item text may be determined. One or more sets of content item text may be selected from among the plurality of sets of content item text based upon the plurality of similarity scores and a plurality of performance metric scores associated with the plurality of sets of content item text. The plurality of performance metric scores may comprise one or more performance metric scores associated with the one or more sets of content item text. The one or more performance metric scores may be higher than the first performance metric score. One or more representations of the one or more sets of content item text may be displayed.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Inventors: Shaunak Mishra, Changwei Hu, Kevin Yen, Manisha Verma, Yifan Hu, Maxim Ivanovich Sviridenko, Avinash Chukka, Max Edward Beech, Chao-Hung Wang, Hua-Ying Tsai, Kamil Michal Zasadzinski, Wei Yu Lin, Yu Tian
  • Patent number: 11990351
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Patent number: 11990430
    Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yu Tsai, Ku-Feng Yang, Wen-Chih Chiou
  • Publication number: 20240160078
    Abstract: A light source device includes a light emitting element and a fluorescent portion. The light emitting element is configured to emit light. The fluorescent portion is disposed on the light emitting element. The fluorescent portion is configured to transform the light into illumination light. In the spectrum of the illuminating light, the energy in red band is in a range from 25% to 45% of the energy in full band.
    Type: Application
    Filed: July 20, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Yu TSAI, Ching-Huan LIAO
  • Publication number: 20240157217
    Abstract: A golf teaching method and a golf teaching system are provided. The golf teaching method includes: configuring image capturing devices and golf simulator to capture swing images and corresponding simulator data records, when a user performs a golf swing; configuring an expert model that includes expert motion information and corresponding correction suggestion information; configuring a computing device to perform an analysis process on the swing images and the simulator data records to divide the golf swing into user motions according to stages and obtaining records of user motion information corresponding to the plurality of stages, and to compare the user motion information with the corresponding expert motion information in each stage through the expert model, and to provide the corresponding correction suggestion information according to a comparison result; and configuring a user interface to provide the correction suggestion information.
    Type: Application
    Filed: April 20, 2023
    Publication date: May 16, 2024
    Inventors: CHENG-HUNG TSAI, CHIA-YU JIH, CHIH-CHUNG CHIEN, LI-LIN LU, SHAO-JUN TAN, WEN-FU LAI
  • Publication number: 20240162208
    Abstract: A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.
    Type: Application
    Filed: December 7, 2022
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Chih-Wei Chang, Fu-Yu Tsai, Bin-Siang Tsai, Chung-Yi Chiu
  • Publication number: 20240161968
    Abstract: A planar transformer is configured on a multi-layer circuit board of a resonant converter. The planar transformer includes multiple layers of primary-side traces, multiple layers of secondary-side traces, and an iron core. The primary-side traces serve as a primary-side coil of the transformer to generate a first direction magnetic flux when the resonant converter operates. The secondary-side traces serve as a secondary-side coil of the transformer to generate a second direction magnetic flux when the resonant converter operates. The primary-side traces and the secondary-side traces surround a first core pillar and the second core pillar, and the primary-side traces and the secondary-side traces are configured in a specific stacked structure on the multi-layer circuit board, so that a magnetomotive force of the planar transformer can maintain balance during the operation of the resonant converter.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Hsun CHIU, Yi-Sheng CHANG, Chun-Yu YANG, Meng-Chi TSAI
  • Publication number: 20240159642
    Abstract: A smoke detector with an anti-insect function includes a substrate, an optical detection module, a top cover, a base and a perforated plate. The substrate has a ring shape region surrounding a central detection region, and a first block structure of the central detection region is protruded from the substrate and higher than an upper surface of the ring shape region. The optical detection module is disposed inside the central detection region. The top cover has a lateral wall. The base is disposed on the substrate and connected to the top cover to cover the optical detection module. The base has a second block structure partly overlapped with the lateral wall to form a guiding channel. The perforated plate is disposed between the lateral wall and the second block structure to prevent an insect from moving into the top cover through the guiding channel.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Applicant: PixArt Imaging Inc.
    Inventors: Yen-Chang Chu, Cheng-Nan Tsai, Chih-Ming Sun, Zhi-Hao Wu, Hung-Yu Lai
  • Patent number: 11984511
    Abstract: A semiconductor device includes a channel structure, a dielectric structure, a gate structure, a first conductive structure, and a second conductive structure. The channel structure has a top surface, a bottom surface, and a sidewall extending from the top surface to the bottom surface. The first conductive structure is disposed on the bottom surface of the channel structure and includes a body portion and at least one convex portion, and a top surface of the convex portion is higher than a top surface of the body portion. The second conductive structure is disposed on the top surface of the channel structure and includes a body portion and at least one convex portion, and a bottom surface of the body portion is higher than a bottom surface of the convex portion.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: May 14, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 11983267
    Abstract: A data processing method based on Trojan circuit detection includes controlling a processor, in a testing stage, to perform following steps: obtaining a plurality of characteristic values corresponding to a logic gate circuit; performing a distribution adjustment operation on the characteristic values to generate a plurality of adjusted characteristic values; and performing classification on the adjusted characteristic values to generate a logic identification result.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: May 14, 2024
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Jian Wei Liao, Ting Yu Lin, Kai Chiang Wu, Jung Che Tsai
  • Patent number: 11985422
    Abstract: The present disclosure provides a dual-lens movement control method, which includes steps as follows. The tracking target is detected through the wide-angle lens, and the final tracking range is calculated; the magnification and the position are determined according to the final tracking range; the separate mode or the alignment mode is determined according to the magnification and the position.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: May 14, 2024
    Assignee: AVer Information Inc.
    Inventors: Te-Yu Liu, Shih-Fu Tsai, Kuo-Hao Huang
  • Publication number: 20240155402
    Abstract: One wireless sensing method includes: generating a measurement request frame, wherein the measurement request frame is configured to carry indication information for phase report from a sensing responder, and sending the measurement request frame to the sensing responder. Another wireless sensing method includes: generating a measurement report frame, wherein the measurement report frame is configured to carry phase information, and sending the measurement report frame to a sensing initiator.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 9, 2024
    Applicant: MEDIATEK INC.
    Inventors: Tsung-Han Tsai, Hsuan-Yu Liu, Shuling Feng