Patents by Inventor Yu Wei Huang

Yu Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12004291
    Abstract: A lens module of reduced size includes a base and an adhesive body. The base includes a first base portion and a second base portion located outside the first base portion. The first base portion is made of plastic and the second base portion is made of metal. The base further comprises a slot. The adhesive body is received in the slot and connects the first base portion and the second base portion. The disclosure also provides an electronic device having the lens module.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: June 4, 2024
    Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN) CO. LTD.
    Inventors: Yu-Shuai Li, Ding-Nan Huang, Jing-Wei Li, Jian-Chao Song
  • Patent number: 12002768
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: June 4, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hao Chang, Po-Chun Lin, Chun-Ti Lu, Zheng-Gang Tsai, Shih-Wei Chen, Chia-Hung Liu, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 12002710
    Abstract: A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: June 4, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsin Chan, Jiing-Feng Yang, Kuan-Wei Huang, Meng-Shu Lin, Yu-Yu Chen, Chia-Wei Wu, Chang-Wen Chen, Wei-Hao Lin, Ching-Yu Chang
  • Patent number: 11999944
    Abstract: A method for promoting growth of a probiotic microorganism includes cultivating the probiotic microorganism in a growth medium containing a fermented culture of lactic acid bacterial strains that include Lactobacillus salivarius subsp. salicinius AP-32 deposited at the China Center for Type Culture Collection (CCTCC) under CCTCC M 2011127, Lactobacillus plantarum LPL28 deposited at the China General Microbiological Culture Collection Center (CGMCC) under CGMCC 17954, Lactobacillus acidophilus TYCA06 deposited at the CGMCC under CGMCC 15210, and Bifidobacterium longum subsp. infantis BLI-02 deposited at the CGMCC under CGMCC 15212.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: June 4, 2024
    Assignee: GLAC BIOTECH CO., LTD.
    Inventors: Hsieh-Hsun Ho, Ching-Wei Chen, Yu-Fen Huang, Cheng-Chi Lin, Chen-Hung Hsu, Tsai-Hsuan Yi, Yu-Wen Chu, Yi-Wei Kuo, Jui-Fen Chen, Shin-Yu Tsai
  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
  • Publication number: 20240175314
    Abstract: A window blind position damping device is applied to a window blind with slat being expanded horizontally, forming a damping to a pull cord effectively when the slat is pulled down at any height, so as to define the height. The window blind position damping device includes a machine part, and an interior of the machine part has a spring scroll wheel and a position damping device which links a pull cord through a provided release idler. A damping shear pillar is vertically disposed on a base plate of the provided machine part, between an outlet of the release idler and an opening. By a provided shear ridge, the damping shear pillar shears an overrun section of the pull cord that passes through, forming the damping and thereby defining and fixing the slat at any height when being expanded.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Inventors: Hsien-Te HUANG, Yu-Wei HUANG
  • Publication number: 20240175854
    Abstract: An air pollution forecast management system including an air quality management device and an Internet of Things (IOT) cloud platform is disclosed. The air quality management device includes a dust particle sensing module being configured to sense gas exhausted from a smoke exhaust flue. The IoT cloud platform is configured to compute, at a second time after a first time, an exhaust gas set of the gas drifting from the first time to the second time by using current-observed meteorological data at the second time, receive a plurality of air-pollution sets at a plurality of geographic locations at the second time, compute a plurality of influencing results of the plurality of air-pollution sets respectively associated with the exhaust gas set, and generate a feedback instruction according to at least one of the plurality of influencing results to control gas emission of the smoke exhaust flue.
    Type: Application
    Filed: February 10, 2023
    Publication date: May 30, 2024
    Inventors: Chao-Kai CHENG, Szu-Wei HUANG, Yu-Wen CHEN, Chung-Hsiang MU
  • Publication number: 20240174512
    Abstract: A MEMS probe and manufacturing method thereof are provided. The method is mainly to form connected first-level, second-level, and third-level pin grooves on both sides of the silicon substrate through an etching process, followed by two electroplating processes to deposit nickel-cobalt-phosphorus alloy in the first-level pin groove to form the tip of the microprobe, and to deposit nickel-cobalt alloy in the second-level pin groove and the third-level pin to form the pin head and pin arm, thereby forming a three-level microprobe. A circuit substrate made of ceramic material is disposed with at least one window, the surface of the circuit substrate adjacent to the window is provided with a plurality of circuit pads, and the circuit substrate is abutted to the pin arm of the microprobe. The silicon substrate is then removed, to form a plurality of cantilever microprobes made of nickel-cobalt-phosphorus alloy and nickel-cobalt alloy on the circuit substrate.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: SHANG-KUANG WU, YU-TSUNG FU, MING-WEI HUANG
  • Patent number: 11996409
    Abstract: A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Xuan Huang, Chia-En Huang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11997266
    Abstract: Methods and apparatus for loop-filter processing of reconstructed video are disclosed. According to one method, multiple CC-ALF (Cross-Component Adaptive Loop Filter) filters are used. Selection of the multiple CC-ALF filters can be signalled in one APS (Adaptation Parameter Set). According to another method, the CC-ALF can be implemented according to the difference between a to-be-process sample and its neighbouring sample.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: May 28, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Yu-Wen Huang, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Shaw-Min Lei
  • Publication number: 20240170397
    Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a low-k dielectric layer over the second dielectric layer, a second dielectric layer on the high resistance layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 23, 2024
    Inventors: Hong-Wei Chan, Yung-Shih Chen, Wen-Sheh Huang, Yu-Hsiang Cheng
  • Publication number: 20240168261
    Abstract: A photographing system lens assembly includes, in order from an object side to an image side: a first lens element, a second lens element, a third lens element and a fourth lens element. Each of the four lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. At least one surface of at least one lens element in the photographing system lens assembly has at least one inflection point. The first lens element has positive refractive power, the object-side surface of the first lens element is convex in a paraxial region thereof, and the image-side surface of the first lens element is convex in a paraxial region thereof. The object-side surface of the second lens element is concave in a paraxial region thereof. The image-side surface of the third lens element is concave in a paraxial region thereof.
    Type: Application
    Filed: March 10, 2023
    Publication date: May 23, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Yu-Tai TSENG, Po-Wei CHEN, I-Hsuan CHEN, Hsin-Hsuan HUANG
  • Publication number: 20240170381
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan CAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20240157890
    Abstract: A vehicle electronic device is provided, including a vehicle window assembly, a first signal element, and a first protective element. The vehicle window assembly comprises a first protective substrate, a second protective substrate, and a display panel. The display panel is disposed between the first protective substrate and the second protective substrate. The first signal element is electrically connected to the display panel. The first protective element covers at least one portion of the first signal element.
    Type: Application
    Filed: September 28, 2023
    Publication date: May 16, 2024
    Inventors: Yu-Chia HUANG, Tsung-Han TSAI, Kuan-Feng LEE, Li-Wei SUNG
  • Patent number: 11985324
    Abstract: Exemplary video processing methods and apparatuses for encoding or decoding a current block by inter prediction are disclosed. Input data of a current block is received and partitioned into sub-partitions and motion refinement is independently performed on each sub-partition. A reference block for each sub-partition is obtained from one or more reference pictures according to an initial motion vector (MV). A refined MV for each sub-partition is derived by searching around the initial MV with N-pixel refinement. One or more boundary pixels of the reference block for a sub-partition is padded for motion compensation of the sub-partition. A final predictor for the current block is generated by performing motion compensation for each sub-partition according to its refined MV. The current block is then encoded or decoded according to the final predictor.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Yu-Cheng Lin, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11983848
    Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: May 14, 2024
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Lung Jen, Pei-Kuei Tsung, Chih-Wei Chen, Yao-Sheng Wang, Shih-Che Chen, Yu-Sheng Lin, Chih-Wen Goo, Shih-Chin Lin, Tsung-Shian Huang, Ying-Chieh Chen
  • Patent number: 11985314
    Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing out-of-bounds nodes in a current picture. An out-of-bounds node is a coding tree node with a block region across a current picture boundary. The video processing method or apparatus determines an inferred splitting type, applies the inferred splitting type to split the out-of-bounds node into child blocks, adaptively splits each child block into one or multiple leaf blocks, and encodes or decodes the leaf blocks in the out-of-bounds node inside the current picture. The inferred splitting type for partitioning out-of-bounds nodes in an inter slice, picture, or tile is the same as the inferred splitting type for partitioning out-of-bounds nodes in an intra slice, picture, or tile.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Publication number: 20240154447
    Abstract: A power system including a first battery pack, a second battery pack, and a power management circuit is disclosed. The first battery pack has a first end and a second end, and has a first battery capacity. The second battery pack has a third end and a fourth end. The third end is coupled to the second end of the first battery pack and provides a low battery voltage. The fourth end is grounded, the second battery pack has a second battery capacity, and the second battery capacity is greater than the first battery capacity. The power management circuit is coupled to the second battery pack to receive the low battery voltage, and provides a component operating voltage to an electronic components based on the low battery voltage.
    Type: Application
    Filed: August 29, 2023
    Publication date: May 9, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Yi-Hsuan Lee, Liang-Cheng Kuo, Chun-Wei Ko, Ya Ju Cheng, Chih Wei Huang, Ywh Woei Yeh, Yu Cheng Lin, Yen Ting Wang
  • Patent number: 11979593
    Abstract: Method and apparatus for affine CPMV or ALF refinement are mentioned. According to this method, statistical data associated with the affine CPMV or ALF refinement are collected over a picture area. Updated parameters for the affine CPMV refinement or the ALF refinement are then derived based on the statistical data, where a process to derive the updated parameters includes performing multiplication using a reduced-precision multiplier for the statistical data. The reduced-precision multiplier truncates at least one bit of the mantissa part. In another embodiment, the process to derive the updated parameters includes performing reciprocal for the statistical data using a lookup table with (m?k)-bit input by truncating k bits from the m-bit mantissa part, and contents of the lookup table includes m-bit outputs. m and k are positive integers.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: May 7, 2024
    Assignee: MEDIATEK INC.
    Inventors: Shih-Chun Chiu, Tzu-Der Chuang, Ching-Yeh Chen, Chun-Chia Chen, Chih-Wei Hsu, Yu-Wen Huang
  • Patent number: D1027976
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 21, 2024
    Assignee: VIVOTEK INC.
    Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung