Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.

Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.

Abstract: An epitaxial structure adapted to a semiconductor pickup element is provided. The semiconductor pickup element has at least one guiding structure and provided with a pickup portion. The epitaxial structure includes a semiconductor layer corresponding to the pickup portion and capable of being picked up by the semiconductor pickup element. The epitaxial structure also includes at least one alignment structure disposed on the semiconductor layer and corresponding to the at least one guiding structure, so that the epitaxial structure and the semiconductor pickup element are positioned relative to each other. The number of the at least one alignment structure matches the number of the at least one guiding structure.

Abstract: A semiconductor structure comprising a first electrode, a second electrode, a phase-change material (PCM) line in contact with and positioned between the first electrode and the second electrode, at least two heater lines positioned between the first electrode and the second electrode, and an isolation layer positioned between the PCM line and the at least two heater lines is provided. A method of forming a semiconductor structure is provided, the method including forming a dielectric isolation layer having a planar top surface over a substrate, forming at least two heater lines over the planar top surface, forming at least one heater-capping dielectric plate over the at least two heater lines, forming a phase-change material (PCM) line over the at least one heater-capping dielectric plate, forming a first electrode and a second electrode, and forming a PCM-capping dielectric plate over the PCM line.

Abstract: A selector structure may include a bottom electrode including a bottom low thermal conductivity (LTC) metal and a first bottom high thermal conductivity (HTC) metal, a first switching film on the bottom electrode and having an electrical resistivity switchable by an electric field, and a first top electrode on the first switching film and including a first top low thermal conductivity (LTC) metal and a first top high thermal conductivity (HTC) metal.

Abstract: A phase change device includes a substrate with a top surface. A heater structure is disposed on the substrate. The heater structure has first and second sidewalls on opposite sides of the heater structure. A phase change element is disposed over the heater structure. The phase change element includes three connected portions. A first portion is disposed over the heater structure. A second portion is disposed over the first sidewall of the heater structure. A third portion is over a first portion of the top surface of the substrate adjacent to and spaced apart from the first sidewall of the heater structure.

Abstract: A phase-change material (PCM) switching device includes: a base dielectric layer over a semiconductor substrate; a first heater element disposed on the base dielectric layer, the first heater element comprising a first metal element characterized by a first coefficient of thermal expansion (CTE); a second heater element disposed on the first heater element, the second heater element comprising a second metal element characterized by a second CTE larger than the first CTE; a first metal pad and a second metal pad; and a PCM region comprising a PCM operable to switch between an amorphous state and a crystalline state in response to heat generated by the first heater element and the second heater element, wherein the PCM region is disposed above a top surface of the second heater element, and an air gap surrounds the first heater element and the second heater element from three sides.

Abstract: A phase-change material (PCM) switching device is provided. The PCM switching device includes: a base dielectric layer over a semiconductor substrate; a heater element embedded in the base dielectric layer, the heater element comprising a first metal element and configured to generate heat in response to a current flowing therethrough; a self-aligned dielectric layer disposed on the heater element, wherein the self-aligned dielectric layer comprises one of an oxide of the first metal element and a nitride of the first metal element, and the self-aligned dielectric layer is horizontally aligned with the heater element; a PCM region disposed on the self-aligned dielectric layer, wherein the PCM region comprises a PCM operable to switch between an amorphous state and a crystalline state in response to the heat generated by the heater element; and two metal pads electrically connected to the PCM region.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.

Abstract: Phase change material (PCM) switches and methods of fabrication thereof that provide improved thermal confinement within a phase change material layer. A PCM switch may include a dielectric capping layer between a heater pad and the phase change material layer of the PCM switch that is laterally-confined such opposing sides of the dielectric capping layer the heater pad may form continuous surfaces extending transverse to the signal transmission pathway across the PCM switch. Heat transfer from the heater pad through the dielectric capping layer to the phase change material layer may be predominantly vertical, with minimal thermal dissipation along a lateral direction. The localized heating of the phase change material may improve the efficiency of the PCM switch enabling lower bias voltages, minimize the formation of regions of intermediate resistivity in the PCM switch, and improve the parasitic capacitance characteristics of the PCM switch.

Abstract: A semiconductor device includes a first capacitor having a ferroelectric film disposed between two electrodes, a second capacitor, having another dielectric film disposed between two electrodes. A first voltage is applied across the first capacitor such that the ferroelectric film is polarized, altering the effective resistance through the device. A second voltage is applied across the first capacitor, such that a leakage current transits the ferroelectric film, and accumulates along an electrode of the second capacitor, and the gate of a transistor, thereby effecting a change to the drain to source resistance of the transistor which may be measured to determine the polarization state of the ferroelectric film.

Abstract: A memory device is provided in various embodiments. The memory device, in those embodiments, has an ovonic threshold switching (OTS) selector comprising multiple layers of OTS materials to achieve a low leakage current and as well as relatively low threshold voltage for the OTS selector. The multiple layers can have at least one layer of low bandgap OTS material and at least one layer of high bandgap OTS material.

Abstract: A method of forming a memory device according to the present disclosure includes forming a trench in a first substrate of a first wafer, depositing a data-storage element in the trench, performing a thermal treatment to the first wafer to improve a crystallization in the data-storage element, forming a first redistribution layer over the first substrate, forming a transistor in a second substrate of a second wafer, forming a second redistribution layer over the second substrate, and bonding the first wafer with the second wafer after the performing of the thermal treatment. The data-storage element is electrically coupled to the transistor through the first and second redistribution layers.

Abstract: Some embodiments relate to an embedded memory device with vertically stacked source, drain and gate connections. The semiconductor memory device includes a substrate and a pillar of channel material extending in a first direction. A bit line is disposed over the pillar of channel material and is coupled to the pillar of channel material, and extends in a second direction that is perpendicular to the first direction. Word lines are on opposite sides of the pillar of channel material and extend in a third direction. The third direction is perpendicular to the second direction. A dielectric layer separates the word lines from the pillar of channel material. Source lines extend in the third direction over the substrate, directly beneath the word lines. Variable resistance memory layers are between the source lines and an outer sidewall of the dielectric layer, laterally surrounding the sidewalls of the pillar of channel material.

Abstract: A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.