Abstract: A method for promoting growth of a probiotic microorganism includes cultivating the probiotic microorganism in a growth medium containing a fermented culture of lactic acid bacterial strains that include Lactobacillus salivarius subsp. salicinius AP-32 deposited at the China Center for Type Culture Collection (CCTCC) under CCTCC M 2011127, Lactobacillus plantarum LPL28 deposited at the China General Microbiological Culture Collection Center (CGMCC) under CGMCC 17954, Lactobacillus acidophilus TYCA06 deposited at the CGMCC under CGMCC 15210, and Bifidobacterium longum subsp. infantis BLI-02 deposited at the CGMCC under CGMCC 15212.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.

Abstract: A semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

Abstract: A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.

Abstract: The present invention provides a method for preventing and/or treating a NSAID-induced gastric ulcer. The method comprises administrating an effective amount of a lactic acid bacterium set to a subject. The lactic acid bacterium set comprises Lactobacillus plantarum GKD7 and Pediococcus acidilactici GKA4.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A vehicle electronic device is provided, including a vehicle window assembly, a first signal element, and a first protective element. The vehicle window assembly comprises a first protective substrate, a second protective substrate, and a display panel. The display panel is disposed between the first protective substrate and the second protective substrate. The first signal element is electrically connected to the display panel. The first protective element covers at least one portion of the first signal element.

Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing out-of-bounds nodes in a current picture. An out-of-bounds node is a coding tree node with a block region across a current picture boundary. The video processing method or apparatus determines an inferred splitting type, applies the inferred splitting type to split the out-of-bounds node into child blocks, adaptively splits each child block into one or multiple leaf blocks, and encodes or decodes the leaf blocks in the out-of-bounds node inside the current picture. The inferred splitting type for partitioning out-of-bounds nodes in an inter slice, picture, or tile is the same as the inferred splitting type for partitioning out-of-bounds nodes in an intra slice, picture, or tile.

Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: Provided is a recombinant microorganism including at least two genes for producing itaconic acid and its derived monomers, and the at least two genes are located on the same expression vector. The at least two genes include one encoding cis-aconitic acid decarboxylase and the other one encoding aconitase, and the genome of the recombinant microorganism includes a gene encoding the molecular chaperone protein GroELS. Also provided is a method for producing itaconic acid by using the microorganism.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: An electronic device includes a monitor stand, a hinge mechanism, and an operation element. The hinge mechanism includes a back plate, a speed reduction assembly, and a friction assembly. The back plate is fixed to the monitor stand. The speed reduction assembly includes an input plate and a speed reduction member. The speed reduction member is arranged on the input plate. The friction assembly is arranged between the back plate and the input plate. The operation element is connected to the speed reduction member. A rotation center of the operation element coincides with an axis of the back plate and the speed reduction member are coaxially arranged.

Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.

Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.

Abstract: A method forming a grating device includes: providing a substrate; entering the substrate into a process chamber; and depositing a grating material on the substrate to form a grating material layer on the substrate. A refractive index of the grating material gradually changes during depositing the grating material in the process chamber. The grating material layer includes a varying refractive index.

Abstract: A development system and a method of an offline software-in-the-loop simulation are disclosed. A common firmware architecture generates a chip control program. The common firmware architecture has an application layer and a hardware abstraction layer. The application layer has a configuration header file and a product program. A processing program required by a peripheral module is added to the hardware abstraction layer during compiling. The chip control program is provided to a controller chip or a circuit simulation software to be executed to control the product-related circuit through controlling the peripheral module.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.

Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.