Patents by Inventor Yu-Wei Yeh

Yu-Wei Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176094
    Abstract: An optical system is provided, including a first module configured to hold a first optical member. The first module includes a first movable portion, a first fixed portion, and a first driving assembly. The first movable portion is configured to connect the first optical member, and is movable relative to the fixed portion. The first driving assembly is configured to drive the first movable portion to move relative to the fixed portion.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Inventors: Chia-Che WU, Chao-Chang HU, Yung-Hsien YEH, Chih-Wei WENG, Chih-Wen CHIANG, Yu-Chiao LO, Sin-Jhong SONG
  • Publication number: 20240176159
    Abstract: An optical system that includes a first module is provided. The first module includes a first movable portion, a first fixed portion, and a first driving assembly. The first movable portion is configured to connect the first optical member, and is movable relative to the first fixed portion. The first driving assembly is configured to drive the first movable portion to move relative to the first fixed portion.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Inventors: Chia-Che WU, Chao-Chang HU, Yung-Hsien YEH, Chih-Wei WENG, Chih-Wen CHIANG, Yu-Chiao LO, Sin-Jhong SONG
  • Publication number: 20240162088
    Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsia-Wei CHEN, Fu-Ting SUNG, Yu-Wen LIAO, Wen-Ting CHU, Fa-Shen JIANG, Tzu-Hsuan YEH
  • Publication number: 20240154447
    Abstract: A power system including a first battery pack, a second battery pack, and a power management circuit is disclosed. The first battery pack has a first end and a second end, and has a first battery capacity. The second battery pack has a third end and a fourth end. The third end is coupled to the second end of the first battery pack and provides a low battery voltage. The fourth end is grounded, the second battery pack has a second battery capacity, and the second battery capacity is greater than the first battery capacity. The power management circuit is coupled to the second battery pack to receive the low battery voltage, and provides a component operating voltage to an electronic components based on the low battery voltage.
    Type: Application
    Filed: August 29, 2023
    Publication date: May 9, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Yi-Hsuan Lee, Liang-Cheng Kuo, Chun-Wei Ko, Ya Ju Cheng, Chih Wei Huang, Ywh Woei Yeh, Yu Cheng Lin, Yen Ting Wang
  • Publication number: 20240155807
    Abstract: A two-phase immersion-type heat dissipation structure having acute-angle notched structures is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate, and a plurality of fins. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other, the non-fin surface is configured to be in contact with a heat source immersed in a two-phase coolant, and the fin surface is connected with the fins. More than half of the fins are functional fins, and at least one side surface of each of the functional fins has first and second surfaces defined thereon and connected to each other. An angle between the first surface and the fin surface is from 80 degrees to 100 degrees, and an angle between the second surface and the fin surface is less than 75 degrees.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Inventors: CHUN-TE WU, CHING-MING YANG, YU-WEI CHIU, TZE-YANG YEH
  • Publication number: 20240155809
    Abstract: A two-phase immersion-type heat dissipation structure having fins for facilitating bubble generation is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate, and a plurality of fins. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other, the non-fin surface is configured to be in contact with a heat source immersed in a two-phase coolant, and the fin surface is connected with the plurality of fins. More than half of the fins are functional fins, and at least one side surface of each of the functional fins and the fin surface have an included angle therebetween that is from 80 degrees to 100 degrees. A center line average roughness (Ra) of the side surface is less than 3 ?m, and a ten-point average roughness (Rz) of the side surface is not less than 12 ?m.
    Type: Application
    Filed: November 6, 2022
    Publication date: May 9, 2024
    Inventors: CHUN-TE WU, CHING-MING YANG, YU-WEI CHIU, TZE-YANG YEH
  • Publication number: 20240155808
    Abstract: A two-phase immersion-cooling heat-dissipation composite structure is provided. The heat-dissipation composite structure includes a heat dissipation base, a plurality of high-thermal-conductivity fins, and at least one high-porosity solid structure. The heat dissipation base has a first surface and a second surface that face away from each other. The second surface of the heat dissipation base is in contact with a heating element immersed in a two-phase coolant. The first surface of the heat dissipation base is connected to the high-thermal-conductivity fins. The at least one high-porosity solid structure is located at the first surface of the heat dissipation base, and is connected and alternately arranged between side walls of two adjacent ones of the high-thermal-conductivity fins. Each of the high-porosity solid structure includes a plurality of closed holes and a plurality of open holes.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Inventors: CHUN-TE WU, CHING-MING YANG, YU-WEI CHIU, TZE-YANG YEH
  • Publication number: 20240142181
    Abstract: A two-phase immersion-type heat dissipation structure having skived fin with high porosity is provided. The two-phase immersion-type heat dissipation structure having skived fin with high porosity includes a porous heat dissipation structure having a total porosity that is equal to or greater than 5%. The porous heat dissipation structure includes a porous substrate and a plurality of porous and skived fins. The porous substrate has a first surface and a second surface that face away from each other. The second surface of the porous substrate is configured to be in contact with a heating element that is immersed in a two-phase coolant. The plurality of porous and skived fins are integrally formed on the first surface of the porous substrate by skiving. A first porosity of the plurality of porous and skived fins is greater than a second porosity of the porous substrate.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Inventors: CHUN-TE WU, CHING-MING YANG, YU-WEI CHIU, TZE-YANG YEH
  • Patent number: 11974371
    Abstract: A light-emitting diode LED driver and a LED driving device including the LED driver are provided. The light-emitting diode LED driver includes a decoding circuit that receives a data signal and decodes the data signal to generate display data used to drive LEDs to emit light and display and a recovered clock signal. Further provided is an encoding circuit that encodes the decoded display data by using the recovered clock signal to generate an encoded data signal, where the data signal is encoded in a first encoding format, and the encoded data signal is encoded in a second encoding format.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: April 30, 2024
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Wang, Che-Wei Yeh, Keko-Chun Liang, Yong-Ren Fang, Yi-Chuan Liu
  • Publication number: 20240128143
    Abstract: Provided are a package structure and a method of forming the same. The method includes: forming an interconnect structure on a substrate; performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening in a same step; forming a protective layer to fill in the first opening and cover the debris layer and the interconnect structure; patterning the protective layer to form a second opening, wherein the second opening is spaced from the debris layer by the protective layer; performing a planarization process on the protective layer to expose a topmost contact pad of the interconnect structure; and performing a mechanical dicing process through the second opening to form a third opening in the substrate and cut the substrate into a plurality of semiconductor dies.
    Type: Application
    Filed: February 1, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Hsieh, Yu-Jin Hu, Hua-Wei Tseng, An-Jhih Su, Der-Chyang Yeh
  • Publication number: 20240130257
    Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.
    Type: Application
    Filed: April 21, 2023
    Publication date: April 18, 2024
    Inventors: Fu-Hai LI, Yi Ching ONG, Hsin Heng WANG, Tsung-Hao YEH, Yu-Wei TING, Kuo-Pin CHANG, Hung-Ju LI, Kuo-Ching HUANG
  • Patent number: 11948837
    Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Fu Yeh, Chin-Lung Chung, Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee
  • Patent number: 11943935
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Publication number: 20230082767
    Abstract: An electronic package is provided and uses a plurality of bonding wires as a shielding structure. The bonding wires are stitch bonded onto a carrier carrying electronic components, such that the problem of the shielding structure peeling off or falling off from the carrier can be avoided due to the fact that the bonding wires are not affected by temperature, humidity and other environmental factors.
    Type: Application
    Filed: November 17, 2022
    Publication date: March 16, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai, Yu-Wei Yeh, Tsung-Hsien Tsai, Chi-Liang Shih, Sheng-Ming Yang, Ping-Hung Liao
  • Publication number: 20230027120
    Abstract: An electronic package is provided, in which a carrier structure provided with electronic components is disposed onto an antenna structure, where a stepped portion is formed at an edge of the antenna structure, so that a shielding body is arranged along a surface of the stepped portion. Therefore, the shielding body only covers a part of the surface of the antenna structure to prevent the shielding body from interfering with operation of the antenna structure.
    Type: Application
    Filed: August 25, 2021
    Publication date: January 26, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shao-Tzu Tang, Wen-Jung Tsai, Chih-Hsien Chiu, Ko-Wei Chang, Yu-Wei Yeh, Yu-Cheng Pai, Chuan-Yi Pan, Chi-Rui Wu
  • Patent number: 11532568
    Abstract: An electronic package is provided and uses a plurality of bonding wires as a shielding structure. The bonding wires are stitch bonded onto a carrier carrying electronic components, such that the problem of the shielding structure peeling off or falling off from the carrier can be avoided due to the fact that the bonding wires are not affected by temperature, humidity and other environmental factors.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: December 20, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai, Yu-Wei Yeh, Tsung-Hsien Tsai, Chi-Liang Shih, Sheng-Ming Yang, Ping-Hung Liao
  • Publication number: 20210375783
    Abstract: An electronic package is provided and uses a plurality of bonding wires as a shielding structure. The bonding wires are stitch bonded onto a carrier carrying electronic components, such that the problem of the shielding structure peeling off or falling off from the carrier can be avoided due to the fact that the bonding wires are not affected by temperature, humidity and other environmental factors.
    Type: Application
    Filed: July 16, 2020
    Publication date: December 2, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai, Yu-Wei Yeh, Tsung-Hsien Tsai, Chi-Liang Shih, Sheng-Ming Yang, Ping-Hung Liao
  • Publication number: 20210351097
    Abstract: An electronic structure and a method for fabricating the same are provided. An electronic component and conductive elements are disposed on a carrier. An encapsulation layer encapsulates the electronic component and the conductive elements. The encapsulation layer has concave portions corresponding in position to the conductive elements. Each of the conductive elements is in no contact with corresponding one of the concave portions.
    Type: Application
    Filed: April 27, 2021
    Publication date: November 11, 2021
    Inventors: Chih-Chiang He, Yu-Wei Yeh, Chia-Yang Chen, Chih-Yi Liao, Chih-Hsien Chiu, Chang-Chao Su
  • Publication number: 20210005524
    Abstract: An electronic structure and a method for fabricating the same are provided. An electronic component and conductive elements are disposed on a carrier. An encapsulation layer encapsulates the electronic component and the conductive elements. The encapsulation layer has concave portions corresponding in position to the conductive elements. Each of the conductive elements is in no contact with corresponding one of the concave portions.
    Type: Application
    Filed: February 18, 2020
    Publication date: January 7, 2021
    Inventors: Chih-Chiang He, Yu-Wei Yeh, Chia-Yang Chen, Chih-Yi Liao, Chih-Hsien Chiu, Chang-Chao Su
  • Patent number: 10818515
    Abstract: The present disclosure provides an electronic package and a method for fabricating the same. A protective layer is formed on a carrier of the electronic component. The electronic component and the protective layer are covered by a covering layer. A through hole is formed in the covering layer and extends through the protective layer, such that a portion of a surface of the carrier is exposed to the through hole. A conductive structure is disposed in the through hole and electrically connected with the carrier. Through the formation of the protective layer, the buffering effect of the protective layer can prevent the laser from directly burning through the covering layer and the protective layer to avoid damages to the carrier.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 27, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Wei Yeh, Yen-Hung Lin, Chih-Yi Liao, Chih-Hsien Chiu