Patents by Inventor Yu Wen

Yu Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11992322
    Abstract: A heart rhythm detection method and system by using radar sensor is capable of collecting an original signal using a radar sensor toward at least one subject, and converting the original signal to a two dimensional image information (i.e., spectrogram) using the concept of image vision. Then, the neural network automatically learns which heartbeat frequency should be focused on and which heartbeat frequency should be filtered out in the two dimensional image information through deep learning, so that the heartbeat frequencies can be extracted effectively.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 28, 2024
    Assignee: IONETWORKS INC.
    Inventors: Jing-Ming Guo, Ting Lin, Chia-Fen Chang, Jeffry Susanto, Yi-Hsiang Lin, Po-Cheng Huang, Yu-Wen Wei
  • Patent number: 11997266
    Abstract: Methods and apparatus for loop-filter processing of reconstructed video are disclosed. According to one method, multiple CC-ALF (Cross-Component Adaptive Loop Filter) filters are used. Selection of the multiple CC-ALF filters can be signalled in one APS (Adaptation Parameter Set). According to another method, the CC-ALF can be implemented according to the difference between a to-be-process sample and its neighbouring sample.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: May 28, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Yu-Wen Huang, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Shaw-Min Lei
  • Patent number: 11993025
    Abstract: A fixing assembly for mounting UV lamps includes a base, a first gear and a plurality of mounting modules. The first gear is arranged on one side of the base; the mounting modules are arranged around the first gear. The mounting module includes a first driving assembly, a second driving assembly and a support frame. The first driving assembly is used to drive the second driving assembly and the support frame to move circumferentially around the first gear in a considerably horizontal plane, and the second driving component is used to drive the support to move back in a considerably vertical direction. The support frame is used for mounting UV lamp. The flexibility of the fixing assembly is improved. The UV lamp may comprehensively irradiate and cure the photosensitive adhesive.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: May 28, 2024
    Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN) CO.LTD.
    Inventors: Yen-Sheng Lin, Yu-Wen Chen
  • Publication number: 20240167920
    Abstract: This disclosure presents a composition for tissue staining and 3D specimen optical clearing, along with a method of making biological material transparent and labeling it simultaneously. The composition includes an amide dye adjuvant, a RI-matching material, a permeating agent, a labeling material, a mixture homogeneity excipient, and a solvent with DMSO. The RI-matching material includes a contrast agent and sugar. The composition has a neutral or acidic pH. The method involves fixing a specimen with a fixative solution and immersing and incubating the specimen in the composition for permeation. This disclosure also presents a kit for rendering biological material transparent. The kit is helpful for experimental animal/human histological studies and cancer staging/tumor differentiation determination.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 23, 2024
    Applicant: JelloX Biotech Inc.
    Inventors: Yu-Han Hsieh, Yi-Wen Lin, YU-CHIEH LIN, YEN-YIN LIN
  • Publication number: 20240165170
    Abstract: The present invention provides a method for preventing and/or treating a NSAID-induced gastric ulcer. The method comprises administrating an effective amount of a lactic acid bacterium set to a subject. The lactic acid bacterium set comprises Lactobacillus plantarum GKD7 and Pediococcus acidilactici GKA4.
    Type: Application
    Filed: March 6, 2023
    Publication date: May 23, 2024
    Applicant: GRAPE KING BIO LTD.
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shin-Wei LIN, You-Shan TSAI, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, Zi-He WU, Yen-Po CHEN, Tzu Chun LIN
  • Publication number: 20240170349
    Abstract: A method of manufacturing a semiconductor structure, comprising: disposing a dielectric layer over a semiconductive wafer defined with a plurality of active regions and a scribe line region surrounding each of the plurality of active regions; forming a plurality of interconnect structures within the dielectric layer, wherein the formation of the plurality of interconnect structures includes forming a plurality of first testing pads within the scribe line region and at least partially exposed through the dielectric layer; and sawing the semiconductive wafer along the scribe line region to form a first interposer and a second interposer, wherein each of the plurality of first testing pads is at least partially removed by the sawing of the semiconductive wafer.
    Type: Application
    Filed: January 15, 2023
    Publication date: May 23, 2024
    Inventors: CHIH-HSUAN TAI, YU-WEI CHIU, KUO WEN CHEN, HSIANG-TAI LU
  • Publication number: 20240172517
    Abstract: A display panel includes: a display substrate, a first barrier wall surrounding a display area, a blocking portion between the first barrier wall and the display area, a first encapsulation layer covering at least the display area, and touch wires. The blocking portion at least partially surrounds the display area. The first encapsulation layer includes a first surface, a second surface and a transition surface connecting the surfaces. On the display substrate, orthographic projections of the touch wires at least partially overlap with an orthographic projection on of the second surface, and are staggered with an orthographic projection of the transition surface; and at least a portion of the orthographic projection of the transition surface is located in a region between a border, away from the display area, of an orthographic projection of the blocking portion and an orthographic projection of a touch wire farthest away from the display area.
    Type: Application
    Filed: July 6, 2021
    Publication date: May 23, 2024
    Inventors: Yang ZENG, Fuqiang YANG, Yu WANG, Yuanqi ZHANG, Ping WEN, Shun ZHANG, Chang LUO, Wei WANG, Tianci CHEN, Yi ZHANG
  • Publication number: 20240169623
    Abstract: Systems and methods for multi-modal image generation are provided. One or more aspects of the systems and methods includes obtaining a text prompt and layout information indicating a target location for an element of the text prompt within an image to be generated and computing a text feature map including a plurality of values corresponding to the element of the text prompt at pixel locations corresponding to the target location. Then the image is generated based on the text feature map using a diffusion model. The generated image includes the element of the text prompt at the target location.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 23, 2024
    Inventors: Yu Zeng, Zhe Lin, Jianming Zhang, Qing Liu, Jason Wen Yong Kuen, John Philip Collomosse
  • Patent number: 11991873
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Yu-Wen Huang, Shu Zhou
  • Patent number: 11986792
    Abstract: The present invention provides a photocuring device, comprising a housing and an ultraviolet (UV) light module, wherein the housing comprises an electroluminescent layer and/or a touch layer and a control module connected to the electroluminescent layer and/or the touch layer by an electrical means. The photocuring device of the invention not only features a low material cost and low production cost, but also allows its display interface and/or operation interface to be provided at any position of the housing of the photocuring device, without limitations in size, shape, or angle. Furthermore, the photocuring device of the invention allows its display interface and/or operation interface to be simplified as needed to facilitate operation and viewing by a manicurist or one who is receiving a manicure.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: May 21, 2024
    Assignee: COSMEX CO., LTD.
    Inventors: Wan-Chieh Hsieh, Ya-Wen Wu, Yu-Ching Li, Wen-Shan Chung
  • Publication number: 20240162088
    Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsia-Wei CHEN, Fu-Ting SUNG, Yu-Wen LIAO, Wen-Ting CHU, Fa-Shen JIANG, Tzu-Hsuan YEH
  • Publication number: 20240162315
    Abstract: A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, an assist gate structure, a tunneling dielectric layer, a floating gate, and an upper gate structure. The assist gate structure is disposed on the substrate. The floating gate includes two opposite first top edges arranged along a first direction, two opposite first sidewalls arranged along the first direction, and two opposite second sidewalls arranged along a second direction different from the first direction. The upper gate structure covers the assist gate structure and the floating gate, where at least one of the first top edges of the floating gate is embedded in the upper gate structure. Portions of the upper gate structure extend beyond the second sidewalls of the floating gate in the second direction, and the portions of the upper gate structure are disposed above the substrate.
    Type: Application
    Filed: December 28, 2022
    Publication date: May 16, 2024
    Applicant: IOTMEMORY TECHNOLOGY INC.
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng
  • Publication number: 20240162317
    Abstract: A non-volatile memory device includes a memory cell including a substrate, a select gate, a control gate, a planar floating gate, a coupling dielectric layer, an erase gate dielectric layer, and an erase gate. The select gate and the control gate are disposed on the substrate and laterally spaced apart from each other, and the control gate includes a non-vertical surface. The planar floating gate includes a lateral tip laterally spaced apart from the control gate. The coupling dielectric layer includes a first thickness (T1). The erase gate dielectric layer covers the non-vertical surface of the control gate and the lateral tip of the planar floating gate, and includes a second thickness (T2). The erase gate covers the erase gate dielectric layer and the lateral tip of the planar floating gate. The first thickness and the second thickness satisfy the following relation: (T2)<(T1)<2(T2).
    Type: Application
    Filed: October 20, 2023
    Publication date: May 16, 2024
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng, Chen-Ming Tsai
  • Publication number: 20240162316
    Abstract: A non-volatile memory device includes at least one memory cell and the memory cell includes a substrate, a select gate, a control gate, a floating gate, and an erase gate. The select gate is disposed on the substrate, and the control gate is disposed on the substrate and laterally spaced apart from the select gate. The control gate comprises a non-vertical surface. The floating gate includes a vertical portion and a horizontal portion. The vertical portion disposed between the select gate and the control gate and includes a first top tip laterally spaced apart from the control gate. The horizontal portion is disposed between the substrate and the control gate, where the horizontal portion includes a lateral tip laterally and vertically spaced apart from the control gate. The erase gate covers the non-vertical surface of the control gate and the lateral tip of the horizontal portion of the floating gate.
    Type: Application
    Filed: October 6, 2023
    Publication date: May 16, 2024
    Inventors: Der-Tsyr Fan, I-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng
  • Patent number: 11983848
    Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: May 14, 2024
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Lung Jen, Pei-Kuei Tsung, Chih-Wei Chen, Yao-Sheng Wang, Shih-Che Chen, Yu-Sheng Lin, Chih-Wen Goo, Shih-Chin Lin, Tsung-Shian Huang, Ying-Chieh Chen
  • Patent number: 11985324
    Abstract: Exemplary video processing methods and apparatuses for encoding or decoding a current block by inter prediction are disclosed. Input data of a current block is received and partitioned into sub-partitions and motion refinement is independently performed on each sub-partition. A reference block for each sub-partition is obtained from one or more reference pictures according to an initial motion vector (MV). A refined MV for each sub-partition is derived by searching around the initial MV with N-pixel refinement. One or more boundary pixels of the reference block for a sub-partition is padded for motion compensation of the sub-partition. A final predictor for the current block is generated by performing motion compensation for each sub-partition according to its refined MV. The current block is then encoded or decoded according to the final predictor.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Yu-Cheng Lin, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11983041
    Abstract: A flexible display, including a stand, a supporting mechanism, a flexible screen, a driving component, a driven component, and a link, is provided. The supporting mechanism is connected to the stand. The flexible screen is attached to the supporting mechanism. The driving component is disposed on the stand. The driven component is disposed on a side of the supporting mechanism distant from the stand. The link has a first end and a second end opposite to the first end. The first end is connected to the driving component, and the second end is connected to the driven component. The driving component drives the driven component through the link to move on a first horizontal plane to drive the supporting mechanism and the flexible screen to transform when the driving component moves between the first horizontal plane and a second horizontal plane that is parallel to the first horizontal plane.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yu-Wen Cheng, Yan-Yu Chen, Chun-Wen Wang, Chung-Lin Hsieh
  • Patent number: 11981753
    Abstract: Disclosed are a peptide compound and an application thereof, and a composition containing the peptide compound. The present invention provides a peptide compound YA-156, and a pharmaceutically acceptable salt, a tautomer, a solvate, a crystal form or a prodrug thereof. The compound has good stability and good activity for Kiss1R.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: May 14, 2024
    Assignee: ShangPharma Innovation Inc.
    Inventors: Yvonne Angell, Yu Wu, Yan Wang, Weimin Liu, Kin Chiu Fong, Jie Wen, Yonghan Hu
  • Patent number: 11985314
    Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing out-of-bounds nodes in a current picture. An out-of-bounds node is a coding tree node with a block region across a current picture boundary. The video processing method or apparatus determines an inferred splitting type, applies the inferred splitting type to split the out-of-bounds node into child blocks, adaptively splits each child block into one or multiple leaf blocks, and encodes or decodes the leaf blocks in the out-of-bounds node inside the current picture. The inferred splitting type for partitioning out-of-bounds nodes in an inter slice, picture, or tile is the same as the inferred splitting type for partitioning out-of-bounds nodes in an intra slice, picture, or tile.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Publication number: 20240151932
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.
    Type: Application
    Filed: March 28, 2023
    Publication date: May 9, 2024
    Inventors: Hsiao-Hsin HU, Chih-Wen CHIANG, Chia-Che WU, Yu-Chiao LO, Yi-Ho CHEN, Chao-Chang HU, Sin-Jhong SONG