Patents by Inventor Yu-Wen Lin
Yu-Wen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240147376Abstract: Apparatus and methods are provided for thermal throttling for UE configured with multi-panel transceiving on FR2. In one novel aspect, the UE prioritizes throttling actions based on signal qualities of each transceiving panel. In one embodiment, the switching to the target panel from the active panel is selected as the highest priority throttling action when the signal quality of the target panel is similar to the active panel. In another embodiment, the UE further determines if the quality of the target panel is sufficient to support mmW transceiving before switching to the target panel. In one embodiment, the UE reduces one or more antennae of an active panel when the signal quality difference between the active panel and the target panel is bigger than a predefined gap threshold.Type: ApplicationFiled: September 22, 2023Publication date: May 2, 2024Inventors: Chih-Chieh Lai, Feng-Wen Weng, Yu-Hung Huang, Chi-Hsiang Lin
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Publication number: 20240138326Abstract: A control method for preparing crop nutrient solution, applied in a regulating device, obtains growth data of crops, and determines a growth state of the crops according to the growth data of the crops. The proportion of the nutrient solution required by the crops is determined according to the growth states of the crops, and the culture solution is adjusted according to the proportion of the nutrient solution. After a preset time period, updated growth state of the crops is determined. When the culture solution does not meet the proportion of the nutrient solution corresponding to the updated growth state, the culture solution is adjusted again until the culture solution meet the proportion of the nutrient solution corresponding to the growth state of the crops.Type: ApplicationFiled: March 28, 2023Publication date: May 2, 2024Inventors: YU-SHAN LIN, CHIEN-HAO SU, KAI-SIANG YOU, YAO-WEN TUNG
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Publication number: 20240143880Abstract: A method includes determining a first timing of a transition sequence of a signal on a first path of an integrated circuit (IC) design, the first timing being based on an IC design signoff voltage, determining a second timing of the transition sequence of the signal on the first path, the second timing being based on the signoff voltage and a first voltage drop along the first path, calculating a first path derating factor based on a timing gap between the first and second timings of the transition sequence, and using the first path derating factor to evaluate the IC design.Type: ApplicationFiled: January 27, 2023Publication date: May 2, 2024Inventors: Yu-Wen LIN, Bogdan TUTUIANU, Florentin DARTU, Wei-Chih HSIEH, Osamu TAKAHASHI
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Publication number: 20240139262Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.Type: ApplicationFiled: October 13, 2023Publication date: May 2, 2024Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, You-Shan TSAI, Zi-He WU
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Patent number: 11966077Abstract: A light emission apparatus includes a laser diode configured to emit a light; a laser driver electrically coupled to the laser diode, the laser driver being configured to drive the laser diode to generate the light; and an optical module arranged to receive the light emitted by the laser diode, the optical module comprising at least one optical element and being configured to adjust the light and emits a transmitting light; wherein the transmitting light emits from the optical module with an illumination angle and the optical module adjusts the light to vary the illumination angle.Type: GrantFiled: July 8, 2019Date of Patent: April 23, 2024Assignee: Artilux, Inc.Inventors: Yun-Chung Na, Chien-Lung Chen, Chieh-Ting Lin, Yu-Yi Hsu, Hui-Wen Chen, Bo-Jiun Chen, Shih-Tai Chuang
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Patent number: 11961769Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.Type: GrantFiled: November 7, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
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Patent number: 11961899Abstract: A semiconductor device includes a gate structure extending along a first lateral direction. The semiconductor device includes a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. The semiconductor device includes an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure.Type: GrantFiled: January 23, 2023Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Chao-Cheng Chen
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Publication number: 20240120388Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.Type: ApplicationFiled: January 18, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Jih-Sheng Yang, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20240121935Abstract: Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. The method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mTorr).Type: ApplicationFiled: January 18, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Y.L. Cheng, Tzu-Wen Pan, Yu-Hsien Lin, Ryan Chia-Jen Chen
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Patent number: 11955338Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.Type: GrantFiled: January 30, 2023Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
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Patent number: 11956948Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.Type: GrantFiled: April 1, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Wen Su, Yu-Kuan Lin, Shih-Hao Lin, Lien-Jung Hung, Ping-Wei Wang
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Publication number: 20240112912Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (Al) or formula (A2): Zr12O8(OH)14(RCO2)18??Formula (A1); or Hf6O4(OH)6(RCO2)10??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.Type: ApplicationFiled: July 28, 2023Publication date: April 4, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Jui-Hsiung LIU, Yu-Fang TSENG, Pin-Chia LIAO, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
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Publication number: 20240113112Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
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Patent number: 11946483Abstract: A fan is provided herein, including a housing, a hub, and a plurality of blades. The housing includes a top case and a bottom case. The hub is rotatably disposed between the top case and the bottom case in an axial direction. The blades extend from the hub in a radial direction, located between the top case and the bottom case. Each of the blades has a proximal end and a distal end. The proximal end is connected to the hub. The distal end is opposite from the proximal end, located at the other side of the blade, having at least one recessed portion. Each of the recessed portions form a passage for air.Type: GrantFiled: May 17, 2023Date of Patent: April 2, 2024Assignee: ACER INCORPORATEDInventors: Jau-Han Ke, Tsung-Ting Chen, Chun-Chieh Wang, Yu-Ming Lin, Cheng-Wen Hsieh, Wen-Neng Liao
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Publication number: 20240097038Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.Type: ApplicationFiled: October 13, 2022Publication date: March 21, 2024Applicant: United Microelectronics Corp.Inventors: Yi Chuen Eng, Tzu-Feng Chang, Teng-Chuan Hu, Yi-Wen Chen, Yu-Hsiang Lin
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Publication number: 20240096630Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.Type: ApplicationFiled: January 12, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Jih-Sheng Yang, Shih-Chieh Chao, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20240094783Abstract: An example computing device includes a first housing portion, a second housing portion moveably connected to the first housing portion, a link to selectively secure the second housing portion to the first housing portion to inhibit movement of the second housing portion relative to the first housing portion, and a shape-memory alloy element to release the link to allow the second housing portion to move relative to the first housing portion.Type: ApplicationFiled: September 15, 2022Publication date: March 21, 2024Inventors: Yu-Wen LIN, Chia-Ming TSAI, Shih-Jen CHOU, John Joseph GRODEN
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Publication number: 20240072170Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Yih-Ann Lin, Chia Ming Liang, Ryan Chia-Jen CHEN
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Publication number: 20240069069Abstract: A probe pin cleaning pad including a foam layer, a cleaning layer, and a polishing layer is provided. The cleaning layer is disposed between the foam layer and the polishing layer. A cleaning method for a probe pin is also provided.Type: ApplicationFiled: November 10, 2023Publication date: February 29, 2024Applicant: Alliance Material Co., Ltd.Inventors: Chun-Fa Chen, Yu-Hsuen Lee, Ching-Wen Hsu, Chao-Hsuan Yang, Ting-Wei Lin
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Patent number: 11914429Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.Type: GrantFiled: March 9, 2023Date of Patent: February 27, 2024Assignee: Acer IncorporatedInventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Yen-Chieh Chiu, Yu-Wen Lin, Yen-Chou Chueh, Po-Yi Lee