Patents by Inventor Yu Yao

Yu Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120313
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
  • Publication number: 20240117362
    Abstract: Embodiments of the present disclosure relate to lipid-PEGylated solid support and phosphoramidites derivatives, methods for preparing the same, and their uses in the delivery of oligonucleotide drugs to the cellular targets.
    Type: Application
    Filed: August 16, 2023
    Publication date: April 11, 2024
    Inventors: Mufa Zou, David Yu, Aldrich N.K. Lau, Ruiming Zou, Wing C. Poon, Gang Zhao, Gengyu Du, Yun-Chiao Yao, Allen Wong, Xiaojun Li
  • Patent number: 11955392
    Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Wen Chang, Yu-Hsien Li, Min-Tar Liu, Yuan-Yao Chang
  • Publication number: 20240113236
    Abstract: A sensing device including a substrate, a circuit layer, and a plurality of sensing units is provided. The circuit layer is disposed on the substrate and includes a plurality of driving circuits. The plurality of sensing units are disposed on the circuit layer, and each of the sensing units includes a supporting part and a sensing part. The supporting part is electrically connected to one of the plurality of driving circuits. The sensing part is electrically connected to the supporting part, and the sensing part is separated from a first cavity by the supporting part and the circuit layer. In a normal direction of the substrate, at least a portion of the supporting part is disposed between the circuit layer and the sensing part.
    Type: Application
    Filed: August 21, 2023
    Publication date: April 4, 2024
    Applicant: Innolux Corporation
    Inventors: I-AN YAO, Yu-Tsung Liu
  • Patent number: 11950431
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: April 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei Chen, Hui-Lin Wang, Yu-Ru Yang, Chin-Fu Lin, Yi-Syun Chou, Chun-Yao Yang
  • Publication number: 20240105865
    Abstract: An optoelectronic device includes a first electrode, a second electrode that is spaced apart from the first electrode, an optoelectronic unit that is disposed between the first electrode and the second electrode, an insulating layer and a driving electrode. The optoelectronic unit includes an optoelectronic stack emitting or absorbing at least two wavelengths of light. The insulating layer is disposed on a lateral side of the optoelectronic stack that extends in a stacking direction of the optoelectronic stack. The driving electrode is disposed on the insulating layer at a location corresponding in position to the optoelectronic unit and is separated from the first and second electrodes.
    Type: Application
    Filed: April 18, 2023
    Publication date: March 28, 2024
    Applicant: National Tsing Hua University
    Inventors: Cheng-Yao LO, Padmanabh Pundrikaksha PANCHAM, Yu-Xin ZENG, Chih-Liang PAN
  • Publication number: 20240102025
    Abstract: The present disclosure provides a gene combination for expressing and producing terrequinone A in Escherichia coli and use thereof. The gene combination includes a tdiAS gene, a tdiBS gene, a tdiCS gene, a tdiDS gene, a tdiES gene, an sfpS gene, an ScCKS gene, and an AtIPKS gene with nucleotide sequences set forth in SEQ ID NOS:1 to 8. In the present disclosure, a recombinant engineered strain capable of producing terrequinone A having anti-cancer activity is obtained by separately constructing recombinant plasmids pC02 and pU03 through the eight genes and transforming the two recombinant plasmids into E. coli. The content of terrequinone A in a fermentation broth thereof is 106.3 mg/L, which has potential application value in the biopharmaceutical field.
    Type: Application
    Filed: May 24, 2023
    Publication date: March 28, 2024
    Inventors: Yongsheng TIAN, Lijuan WANG, Yongdong DENG, Quanhong YAO, Rihe PENG, Jianjie GAO, Zhenjun LI, Wenhui ZHANG, Bo WANG, Jing XU, Yu WANG, Xiaoyan FU, Hongjuan HAN
  • Patent number: 11942396
    Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 26, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Heng-Chieh Chien, Shu-Jung Yang, Yu-Min Lin, Chih-Yao Wang, Yu-Lin Chao
  • Publication number: 20240092817
    Abstract: Embodiments of the present application relate to polymers used as polymeric polyvalent hub for liquid phase oligonucleotide synthesis. Methods for making an oligonucleotide by liquid phase oligonucleotide synthesis using the polyvalent hub are also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 21, 2024
    Inventors: Gaomai Yang, Yun-Chiao Yao, David Yu, Aldrich N.K. Lau
  • Publication number: 20240095597
    Abstract: A method for generating additional training data for training a machine learning algorithm is disclosed. The method includes (i) providing training data for training the machine learning algorithm, wherein the training data includes labeled sensor data from at least one sensor, (ii) transforming the training data for training the machine learning algorithm in a graph structure, wherein nodes in the graph structure represent objects represented in the corresponding sensor data, and wherein a starting node of the graph structure represents the position of the at least one sensor with respect to the objects represented in the corresponding sensor data, and (iii) generating additional training data for training the machine learning model by modifying the graph structure.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 21, 2024
    Inventors: Eitan Kosman, Amulya Hiremath, Barbara Rakitsch, Gonca Guersun, Joerg Wagner, Michael Herman, Yu Yao
  • Patent number: 11936235
    Abstract: The present application relates to a method and apparatus of power distribution control for power module and a power module device. The method includes: obtaining temperature data of target devices in two or more power modules; analyzing whether the power modules are operating at full power when the temperature data of the target devices meets a preset temperature fault condition; and adjusting operating parameters of the power modules based on the temperature data when the power modules are not operating at full power.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: March 19, 2024
    Assignee: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Huaisen Zhang, Yuan Yao, Meng Li, Weichen He, Guiying Lin, Yu Yan
  • Publication number: 20240087974
    Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Lin, Chin-Hua Wang, Shu-Shen Yeh, Chien-Hung Chen, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240084028
    Abstract: Provided herein are tetravalent antibodies that specifically bind to human PSGL-1. Unlike bivalent antibodies, these tetravalent antibodies contain a dimer of two monomers, with each monomer comprising two light chain variable (VL) domains and two heavy chain variable (VH) domains. This format allows for cross-linker/FcR-expressing cell-independent tetravalent antibodies against PSGL-1 that show enhanced efficacy as compared to bivalent PSGL-1 antibodies. These tetravalent antibodies can be used in a variety of diagnostic and therapeutic methods, including without limitation treating T-cell mediated inflammatory diseases, transplantations, and transfusions.
    Type: Application
    Filed: March 13, 2023
    Publication date: March 14, 2024
    Inventors: Rong-Hwa LIN, Shih-Yao LIN, Yu-Ying TSAI
  • Publication number: 20240088095
    Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
  • Publication number: 20240083918
    Abstract: Disclosed are compounds of Formula (I), methods of using the compounds for inhibiting ALK2 activity and pharmaceutical compositions comprising such compounds. The compounds are useful in treating, preventing or ameliorating diseases or disorders associated with ALK2 activity such as cancer.
    Type: Application
    Filed: October 31, 2023
    Publication date: March 14, 2024
    Inventors: Jun Pan, Yu Bai, Liangxing Wu, Wenqing Yao
  • Publication number: 20240082640
    Abstract: An exercise intensity assessing system includes a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser exercises. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database for being diagnosed and analyzed by a fitness instructor. The cloud database obtains a forecasted watt value corresponding to the physiological information, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 14, 2024
    Applicant: EHUNTSUN HEALTH TECHNOLOGY CO., LTD.
    Inventors: Chao-Chuan CHEN, Han-Pin HO, Jong-Shyan WANG, Yu-Ting LIN, Chi-Yao CHIANG, Yu-Liang LIN
  • Publication number: 20240088063
    Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240089607
    Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.
    Type: Application
    Filed: May 29, 2023
    Publication date: March 14, 2024
    Applicant: HTC Corporation
    Inventors: Chao Shuan Huang, Sheng-Long Wu, Yu-Jui Hsu, Shih-Yao Tsai, Tun-Hao Chao, Sen-Lin Chung, Chih Pin Chung, Chih-Yuan Chien, Shih Hong Sun
  • Publication number: 20240082642
    Abstract: An intelligent exercise intensity assessing system includes an exercise testing machine, a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser operates the exercise testing machine. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database. The cloud database analyzes the physiological information to obtain a corresponding forecasted watt value, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 14, 2024
    Applicant: EHUNTSUN HEALTH TECHNOLOGY CO., LTD.
    Inventors: Chao-Chuan CHEN, Han-Pin HO, Jong-Shyan WANG, Yu-Ting LIN, Chi-Yao CHIANG, Yu-Liang LIN
  • Publication number: 20240085808
    Abstract: A particle removal method includes loading a particle attracting member with a coating layer into a processing chamber of a processing apparatus. The processing chamber is configured to perform a lithography exposure process on a semiconductor wafer. The method also includes fixing the particle attracting member on a reticle holder in the processing chamber in a cleaning cycle, attracting particles in the processing chamber by the coating layer of the particle attracting member due to a potential difference between the particles and the coating layer, and loading the particle attracting member with the coating layer and the attracted particles out of the processing chamber, after the cleaning cycle. The method also includes loading the semiconductor wafer into the processing chamber, and performing the lithography exposure process on the semiconductor wafer in the processing chamber using a reticle fixed on the reticle holder after the cleaning cycle.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Chih-Yuan YAO, Yu-Yu CHEN, Hsiang-Lung TSOU