Abstract: Built-In-Logic-Block-Observation registers BILBO are coupled to the output of a Control-Read-Only-Memory CROM in the write-state-machine of a flash EPROM. The Built-In-Logic-Block-Observation registers BILBO include master/slave latches M/SL, shadow latches SHL, and other logic circuitry that enable the various modes of operation required for pulse timing and for signature analysis. During operation a pre-defined FLASH command sequence requests a Control-Read-Only-Memory CROM signature analysis that executes a set of instructions causing the Built-In-Logic-Block-Observation registers BILBO to be placed in the Multiple-Input-Signature-Register Mode and that steps through the Control-Read-Only-Memory CROM until all valid addresses have been evaluated. The resultant Control-Read-Only-Memory CROM signature is then scanned out and verified. The invention eliminates the need for a separate stand-alone Linear-Feedback-Shift-Register LFSR used for pulse timing.

Abstract: The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro-instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder with BILBO control (MID/BC), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and a subroutine stack (SS) to allow function calls. A program counter (PC) takes an index signal from the micro-instruction decoder with BILBO control (MID/BC) and a signal from the program counter multiplexer (PCM), and from those signal, generates a next microcode address. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip.

Abstract: The on-chip endurance test (Autocycle) and the parametric characterization test (Auto VccMax/Min) of this invention save test time and hardware by performance automatically on the memory chip upon transmittal of a single command (CONTROL CODE) to the chip from the tester. The automated test procedures of this invention run faster because the on-chip tester requires fewer externally issued commands (CONTROL CODEs) and requires fewer external status checks. The procedures of this invention permit the external tester to have a smaller number of input/output pins (CONTROL), decreasing the cost of the external test hardware. Specifically, the endurance test (Autocycle), automatically cycles the memory chip through any combination of programming, erasing, and/or compaction operations until either a failure has been detected or the required number of the test cycles has been completed.