Abstract: Provided is an isolated binding protein including an antigen binding domain binding to an NS1 protein, and comprising specific heavy chain CDR and light chain CDR. The binding protein can specifically identify and bind to NS1, and has relatively high sensitivity and specificity, so as to detect dengue virus. Moreover, the binding protein does not need to be produced by injecting hybridoma cells into mouse peritoneal cavity, while simplifying production, thus stabilizing antibody functionality.

Abstract: A process for treating aged oil by electron beam irradiation is disclosed, comprising the following steps: step 1, homogenizing the aged oil and then feeding the aged oil into a distributor; step 2, forming a liquid layer having a certain thickness on the distributor; step 3, installing and debugging an electron beam irradiation device on the distributor; step 4, installing and debugging a phased-array microwave emitter on the distributor after installing and debugging the electron beam irradiation device; step 5, turning on the electron beam irradiation device and the phased-array microwave emitter; and step 6, dividing the treated aged oil and then allowing the aged oil after dividing to enter an oil pool and a water pool for standing. Oil flows out from an upper layer of the oil pool, a lower layer of the oil pool flows back to an aged oil storage pool.

Abstract: Disclosed are a distributed quantum imaging method, apparatus and system, and a computer-readable storage medium. The distributed quantum imaging system comprises a plurality of laser devices that are placed at different spatial positions, a plurality of spatial light modulators, a detector and an imaging processor, wherein each laser device uniquely corresponds to one spatial light modulator.

Abstract: A method for preparing isophorone diisocyanate by (1) reacting isophorone with hydrogen cyanide in the presence of a catalyst to obtain isophorone nitrile; (2) reacting the isophorone nitrile obtained in step (1) with ammonia gas and hydrogen in the presence of a catalyst to obtain isophorone diamine; and (3) subjecting the isophorone diamine to a phosgenation reaction to obtain the isophorone diisocyanate, wherein the content of impurities containing a secondary amine group in the isophorone diamine that undergoes the phosgenation reaction in step (3) is ?0.5 wt. The method reduces the content of hydrolyzed chlorine in the isophorone diisocyanate product, improves the yellowing resistance of the product, and the harm due to presence of hydrolyzed chlorine in the product is reduced.

Abstract: Disclosed is a rock similar material satisfying a water-induced strength degradation characteristic and a preparation method and use thereof. The rock similar material satisfying the water-induced strength degradation characteristic includes an aggregate, a cementing material, and an additive, where the aggregate includes quartz sand, barite powder, and bentonite, and the cementing material includes cement and gypsum.

Abstract: Disclosed are a rock similar material satisfying a water-induced strength degradation characteristic and a preparation method and use thereof. The rock similar material satisfying the water-induced strength degradation characteristic includes an aggregate, a cementing material, and an additive, where the aggregate includes quartz sand, barite powder, and bentonite, and the cementing material includes cement and gypsum.

Abstract: An optimal design method and system for slope reinforcement with anti-slide piles includes: modeling a slope type to obtain a three-dimensional (3D) slope numerical calculation model; establishing different numerical calculation models for anti-slide piles according to different reinforcement schemes of the anti-slide piles; determining optimization indexes through a coupling analysis of the 3D slope numerical calculation model and the anti-slide pile numerical calculation model; calculating a comprehensive optimization value according to the optimization index; determining an optimal anti-slide pile reinforcement scheme according to the comprehensive optimization value, and determining whether the optimal anti-slide pile reinforcement scheme meets the optimization objective; and carrying out slope reinforcement according to the optimal anti-slide pile reinforcement scheme if yes.

Abstract: The present disclosure provides an optimal design method and system for slope reinforcement with anti-slide piles. The method includes: modeling a slope type to obtain a three-dimensional (3D) slope numerical calculation model; establishing different numerical calculation models for anti-slide piles according to different reinforcement schemes of the anti-slide piles; determining optimization indexes through a coupling analysis of the 3D slope numerical calculation model and the anti-slide pile numerical calculation model; calculating a comprehensive optimization value according to the optimization index; determining an optimal anti-slide pile reinforcement scheme according to the comprehensive optimization value, and determining whether the optimal anti-slide pile reinforcement scheme meets the optimization objective; and carrying out slope reinforcement according to the optimal anti-slide pile reinforcement scheme if yes.

Abstract: Provided is a power consumption reduction type power converter. For example, such a power converter includes a regulator configured to convert a power voltage into an operation power of a main integrated circuit (IC), a mode detecting pin configured to detect a voltage level of the operation power, wherein the detected voltage level indicates a disable mode or an enable mode, a mode signal output circuit connected to the mode detecting pin, configured to output a mode converting signal, and a switching controller configured to block or connect a power route according to the mode converting signal to supply or block the operation power from being provided to the main IC, wherein the mode detecting pin is connected to a first switch and a first capacitor to perform a charging or a discharging operation of the first capacitor according to a switching operation of the first switch.

Abstract: A high voltage start-up circuit includes a power supply terminal configured to supply power, a latch unit connected to the power supply terminal and comprising a first P-type Metal-Oxide-Semiconductor (PMOS) transistor, a first N-type metal-oxide semiconductor (NMOS) transistor connected to the first PMOS transistor, a second PMOS transistor, and a second NMOS transistor connected to the second PMOS transistor, wherein the transistors form a latch structure, a charge sharing unit comprising a first capacitor configured to supply a first voltage to a drain of the second PMOS transistor and a second capacitor configured to supply a second voltage to a drain of the first PMOS transistor, and a switching unit configured to form a current path that charges an external capacitor using a voltage supplied from the power supply terminal as a power voltage, based on the first voltage and the second voltage.

Abstract: A high voltage start-up circuit includes a power supply terminal configured to supply power, a latch unit connected to the power supply terminal and comprising a first P-type Metal-Oxide-Semiconductor (PMOS) transistor, a first N-type metal-oxide semiconductor (NMOS) transistor connected to the first PMOS transistor, a second PMOS transistor, and a second NMOS transistor connected to the second PMOS transistor, wherein the transistors form a latch structure, a charge sharing unit comprising a first capacitor configured to supply a first voltage to a drain of the second PMOS transistor and a second capacitor configured to supply a second voltage to a drain of the first PMOS transistor, and a switching unit configured to form a current path that charges an external capacitor using a voltage supplied from the power supply terminal as a power voltage, based on the first voltage and the second voltage.

Abstract: A circuit for adjusting a frequency of an AC direct lighting apparatus is provided. The circuit may include a reference voltage generation unit configured to receive a dimming voltage having a first frequency and a first voltage range, and generate a reference voltage having a second voltage range, a sensing section determining unit configured to generate first and second section reference voltages based on the reference voltage, and determine a driving current sensing section using the first and second section reference voltages, and a driving signal generation unit configured to generate a switching device driving signal having a second frequency through the determined driving current sensing section.

Abstract: An apparatus to drive a multi-channel light emitting diode (LED) array includes switching transistors connected to LED strings of the multi-channel LED array, error amplifiers connected to the switching transistors, each of the error amplifiers being configured to control current flowing through the LED string to have a target magnitude, and overheating protection circuits connected to the switching transistors, each of the overheating protection circuits being configured to regulate current flowing through a respective switching transistor to have a magnitude less than or equal to the target magnitude.

Abstract: There is provided a power supply device sensing an AC-off state. The power supply device includes a rectifier configured to rectify AC power into DC power, a transformer configured to supply output voltage by converting voltage of the DC power rectified by the rectifier, and a Pulse Width Modulation (PWM) control module configured to output voltage by switching a power switching device connected to the transformer, configured to drive the power supply device by connecting power of an HV pin to a VCC pin, and configured to determine an AC-off state by sensing voltage rectified by the rectifier.

Abstract: The present examples relate to a power factor correction device, a power factor correction method, and a corresponding converter, in which when an input signal inputted into the converter is changed, a reference signal is also changed to fit to the input signal in consideration of only the frequency and the phase of the input signal. Thus, even without a specifically designated control circuit, examples make it possible to improve power factor correction and Total Harmonic Distortion (THD) and to reduce the size of a semiconductor chip, and examples are potentially used for a device receiving waveforms other than a sine wave.

Abstract: An apparatus to drive a multi-channel light emitting diode (LED) array includes switching transistors connected to LED strings of the multi-channel LED array, error amplifiers connected to the switching transistors, each of the error amplifiers being configured to control current flowing through the LED string to have a target magnitude, and overheating protection circuits connected to the switching transistors, each of the overheating protection circuits being configured to regulate current flowing through a respective switching transistor to have a magnitude less than or equal to the target magnitude.

Abstract: A gate off delay compensation circuit includes a sensing interval determiner configured to determine an interval in which a driving voltage corresponds to a first and second level of a reference voltage as a driving voltage sensing interval, a driving voltage excess interval determiner configured to determine a driving voltage excess interval defined as an interval in which the driving voltage is larger than the reference voltage and a driving voltage period determiner configured to determine a period of the driving voltage based on the driving voltage sensing interval and the driving voltage excess interval. Therefore, a gate off delay compensation circuit 100 decreases an average driving current and an average driving voltage and allows decrease of a variation of a driving current according to a change of a input voltage VIN.

Abstract: A power factor correction controlling circuit includes a control signal providing circuit configured to provide a control signal associated with a feedback signal, the feedback signal being controlled based on a bias signal, a pulse width modulation signal controlling circuit configured to control a pulse width modulation signal based on one of first and second bias signals and a power factor controlling circuit configured to provide a power factor control signal when an amplitude of the pulse width modulation signal reaches that of the power factor control signal. Such a circuit Is able to operate stably, regardless of a load condition and an input voltage condition.

Abstract: A switch control circuit for controlling an average current flowing into a load through a current control switch that is series-coupled to an input power and the load includes a sensing unit configured to measure a current flowing into the load, a folder unit configured to fold a sensing signal related to the measured current based on a first reference voltage to generate first and second folder output signals based on an initialization voltage, the first and second folder output signals being symmetric to each other, a comparison unit configured to compare the generated first and second folder output signals and a control unit configured to control an operation of the current control switch according to a comparison result in the comparison unit. Such a switch control circuit integrates and compares a sensing signal and a reference signal to effectively perform an average current control.

Abstract: A reference signal generating circuit is provided that generates a reference signal corresponding to an input signal for power factor compensation of a power converter. The reference signal generating circuit includes a detector sampling the input signal according to a reference clock to detect and hold the maximum input signal and a phase measuring unit measuring a phase of the sampled input signal based on the sampled input signal and the detected maximum input signal. The circuit also includes a reference signal generating unit configured to generate a reference signal having a specific value in response to the measured phase.