Abstract: A method for compressing multiple original convolution parameters into a convolution operation chip includes steps of: determining a range of the original convolution parameters; setting an effective bit number for the range; setting a representative value, wherein the representative value is within the range; calculating differential values between the original convolution parameters and the representative value; quantifying the differential values to a minimum effective bit to obtain a plurality of compressed convolution parameters; and transmitting the effective bit number, the representative value and the compressed convolution parameters to the convolution operation chip.

Abstract: A method for compressing multiple original convolution parameters into a convolution operation chip includes steps of: determining a range of the original convolution parameters; setting an effective bit number for the range; setting a representative value, wherein the representative value is within the range; calculating differential values between the original convolution parameters and the representative value; quantifying the differential values to a minimum effective bit to obtain a plurality of compressed convolution parameters; and transmitting the effective bit number, the representative value and the compressed convolution parameters to the convolution operation chip.

Abstract: A convolution operation device includes a convolution operation module, a memory, a scale control module and a scaling unit. The convolution operation module outputs a plurality of convolution operation results containing fractional parts. The memory is coupled to the convolution operation module for receiving and storing the convolution operation results containing the fractional parts, and outputs a plurality of convolution operation input values containing fractional parts. The scale control module is coupled to the convolution operation module and generates a scaling signal according to a total scale of the convolution operation results containing the fractional parts.

Abstract: A convolution operation method includes the following steps of: performing convolution operations for data inputted in channels, respectively, so as to output a plurality of convolution results; and alternately summing the convolution results of the channels in order so as to output a sum result. A convolution operation device executing the convolution operation method is also disclosed.

Abstract: A buffer device includes input lines, an input buffer unit and a remapping unit. The input lines are coupled to a memory and configured to be inputted with data from the memory in a current clock. The input buffer unit is coupled to the input lines and configured to buffer one part of the inputted data and output the part of the inputted data in a later clock. The remapping unit is coupled to the input lines and the input buffer unit, and configured to generate remap data for a convolution operation according to the data on the input lines and the output of the input buffer unit in the current clock. A convolution operation method for a data stream is also disclosed.

Abstract: The present invention relates to a changeable combined mechanical key, belonging to the technical field of key structures of encryption locks. The changeable combined mechanical key includes a bracket detachably connected to an end of a key handle, and a protective cover detachably connected to the end of the key handle and a key-shaped component. The present invention achieves anti-theft and duplication-preventing purposes for a key, and has unique advantages in many important fields such as safety boxes, important military places, banks, household intelligent anti-theft locks, and any other fields that require secrecy security. Unlike an electronic key that is easy to cause a problem due to an electronic circuit device and software and so on, the present invention, which is irreplaceable and has changed a machining process of a traditional mechanical key, saves energy and reduces consumption, and has a broad application prospect.

Abstract: A pooling operation method for a convolutional neural network includes the following steps of: reading multiple new data in at least one column of a pooling window; performing a first pooling operation with the new data to generate at least a pooling result column; storing the pooling result column in a buffer; and performing a second pooling operation with the pooling result column and at least a preceding pooling result column stored in the buffer to generate a pooling result of the pooling window. The first pooling operation and the second pooling operation are max pooling operations.

Abstract: An operation method for a convolutional neural network includes the following steps of: performing an add operation with a plurality of input data to output an accumulated result; performing a bit-shift operation with the accumulated result to output a shifted result; and performing a weight-scaling operation with the shifted result to output a weighted result. Herein, a weighting factor of the weight-scaling operation is determined according to the amount of input data, the amount of right-shifting bits in the bit-shift operation, and a scaled weight value of a consecutive layer in the convolutional neural network.

Abstract: A buffer device includes input lines, an input buffer unit and a remapping unit. The input lines are coupled to a memory and configured to be inputted with data from the memory in a current clock. The input buffer unit is coupled to the input lines and configured to buffer one part of the inputted data and output the part of the inputted data in a later clock. The remapping unit is coupled to the input lines and the input buffer unit, and configured to generate remap data for a convolution operation according to the data on the input lines and the output of the input buffer unit in the current clock. A convolution operation method for a data stream is also disclosed.

Abstract: A convolution operation method includes the following steps of: decomposing a large convolution operation region to multiple small convolution operation regions; the small convolution operation regions perform convolution operations so as to generate partial results, respectively; and summing the partial results as a convolution operation result of the large convolution operation region. A convolution operation device capable of supporting the convolution operation method is also disclosed.

Abstract: A convolution operation method includes the following steps of: performing convolution operations for data inputted in channels, respectively, so as to output a plurality of convolution results; and alternately summing the convolution results of the channels in order so as to output a sum result. A convolution operation device executing the convolution operation method is also disclosed.

Abstract: A convolution operation device includes a convolution calculation module, a memory and a buffer device. The convolution calculation module has a plurality of convolution units, and each convolution unit performs a convolution operation according to a filter and a plurality of current data, and remains a part of the current data after the convolution operation. The buffer device is coupled to the memory and the convolution calculation module for retrieving a plurality of new data from the memory and inputting the new data to each of the convolution units. The new data are not duplicated with the current data. A convolution operation method is also disclosed.

Abstract: A multi-layer artificial neural network having at least one high-speed communication interface and N computational layers is provided. N is an integer larger than 1. The N computational layers are serially connected via the at least one high-speed communication interface. Each of the N computational layers respectively includes a computation circuit and a local memory. The local memory is configured to store input data and learnable parameters for the computation circuit. The computation circuit in the ith computational layer provides its computation results, via the at least one high-speed communication interface, to the local memory in the (i+1)th computational layer as the input data for the computation circuit in the (i+1)th computational layer, wherein i is an integer index ranging from 1 to (N?1).

Abstract: The present invention relates to a changeable combined mechanical key, belonging to the technical field of key structures of encryption locks. The changeable combined mechanical key includes a bracket detachably connected to an end of a key handle, and a protective cover detachably connected to the end of the key handle and a key-shaped component. The present invention achieves anti-theft and duplication-preventing purposes for a key, and has unique advantages in many important fields such as safety boxes, important military places, banks, household intelligent anti-theft locks, and any other fields that require secrecy security. Unlike an electronic key that is easy to cause a problem due to an electronic circuit device and software and so on, the present invention, which is irreplaceable and has changed a machining process of a traditional mechanical key, saves energy and reduces consumption, and has a broad application prospect.

Abstract: This application provides a recombinant expression cassette for expressing the H subunit of Mg-chelatase, a plant gene product that is newly identified as an abscisic acid receptor. Also provided are a transgenic plant with drought-resistance and a method for producing such plants.