Patents by Inventor Yuan-Hsiang Lung
Yuan-Hsiang Lung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9941125Abstract: A method of patterning a substrate includes forming a hard mask layer over the substrate; forming a first material layer over the hard mask layer; and forming a trench in the first material layer. The method further includes treating the hard mask layer with an ion beam through the trench. An etching rate of a treated portion of the hard mask layer reduces with respect to an etching process while an etching rate of untreated portions of the hard mask layer remains substantially unchanged with respect to the etching process. After the treating of the hard mask layer, the method further includes removing the first material layer and removing the untreated portions of the hard mask layer with the etching process, thereby forming a hard mask over the substrate. The method further includes etching the substrate with the hard mask as an etch mask.Type: GrantFiled: August 31, 2015Date of Patent: April 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Lin Yang, Hua Feng Chen, Kuei-Shun Chen, Min-Yann Hsieh, Po-Hsueh Li, Shih-Chi Fu, Yuan-Hsiang Lung, Yan-Tso Tsai
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Publication number: 20180096090Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: ApplicationFiled: January 20, 2017Publication date: April 5, 2018Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
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Patent number: 9754064Abstract: An IC design method includes: receiving a first layout including a first pattern; receiving a second layout including a second pattern, the first pattern separated from the second pattern when overlapping the first layout and the second layout; providing a cut pattern between the first pattern and the second pattern and overlapping the first pattern when overlapping the first layout, the second layout and the cut pattern; and providing a jog extending from the cut pattern to further overlap the first pattern with a length when a spacing between the second pattern and an edge of the cut pattern overlapping the first pattern is lower than a predetermined value, in which a ratio of the length of the jog to the spacing between the second pattern and the edge of the cut pattern overlapping the first pattern is in a range of 1/5 to 1/1.Type: GrantFiled: October 5, 2016Date of Patent: September 5, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chuan-Fang Su, Kun-Zhi Chung, Yuan-Hsiang Lung
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Publication number: 20170062222Abstract: A method of patterning a substrate includes forming a hard mask layer over the substrate; forming a first material layer over the hard mask layer; and forming a trench in the first material layer. The method further includes treating the hard mask layer with an ion beam through the trench. An etching rate of a treated portion of the hard mask layer reduces with respect to an etching process while an etching rate of untreated portions of the hard mask layer remains substantially unchanged with respect to the etching process. After the treating of the hard mask layer, the method further includes removing the first material layer and removing the untreated portions of the hard mask layer with the etching process, thereby forming a hard mask over the substrate. The method further includes etching the substrate with the hard mask as an etch mask.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Tsung-Lin Yang, Hua Feng Chen, Kuei-Shun Chen, Min-Yann Hsieh, Po-Hsueh Li, Shih-Chi Fu, Yuan-Hsiang Lung, Yan-Tso Tsai
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Publication number: 20170024507Abstract: An IC design method includes: receiving a first layout including a first pattern; receiving a second layout including a second pattern, the first pattern separated from the second pattern when overlapping the first layout and the second layout; providing a cut pattern between the first pattern and the second pattern and overlapping the first pattern when overlapping the first layout, the second layout and the cut pattern; and providing a jog extending from the cut pattern to further overlap the first pattern with a length when a spacing between the second pattern and an edge of the cut pattern overlapping the first pattern is lower than a predetermined value, in which a ratio of the length of the jog to the spacing between the second pattern and the edge of the cut pattern overlapping the first pattern is in a range of 1/5 to 1/1.Type: ApplicationFiled: October 5, 2016Publication date: January 26, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chuan-Fang SU, Kun-Zhi CHUNG, Yuan-Hsiang LUNG
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Patent number: 9477804Abstract: An IC design method includes: receiving a first layout including a first pattern; receiving a second layout including a second pattern, the first pattern separated from the second pattern when overlapping the first layout and the second layout; providing a cut pattern between the first pattern and the second pattern and overlapping the first pattern when overlapping the first layout, the second layout and the cut pattern; and providing a jog extending from the cut pattern to further overlap the first pattern with a length when a spacing between the second pattern and an edge of the cut pattern overlapping the first pattern is lower than a predetermined value, in which a ratio of the length of the jog to the spacing between the second pattern and the edge of the cut pattern overlapping the first pattern is in a range of 1/5 to 1/1.Type: GrantFiled: January 20, 2015Date of Patent: October 25, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chuan-Fang Su, Kun-Zhi Chung, Yuan-Hsiang Lung
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Publication number: 20160210395Abstract: An IC design method includes: receiving a first layout including a first pattern; receiving a second layout including a second pattern, the first pattern separated from the second pattern when overlapping the first layout and the second layout; providing a cut pattern between the first pattern and the second pattern and overlapping the first pattern when overlapping the first layout, the second layout and the cut pattern; and providing a jog extending from the cut pattern to further overlap the first pattern with a length when a spacing between the second pattern and an edge of the cut pattern overlapping the first pattern is lower than a predetermined value, in which a ratio of the length of the jog to the spacing between the second pattern and the edge of the cut pattern overlapping the first pattern is in a range of 1/5 to 1/1.Type: ApplicationFiled: January 20, 2015Publication date: July 21, 2016Inventors: Chuan-Fang SU, Kun-Zhi CHUNG, Yuan-Hsiang LUNG
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Patent number: 8850369Abstract: A method for optimizing masks used for forming conductive features and a method for creating the mask features on an IC device are disclosed. An exemplary embodiment includes receiving a design database including a plurality of conductive features. First and second features suitable for joining are identified from the plurality of conductive features. A joined feature corresponding to the first and the second features is characterized. A cut shape configured to separate the first and second features from the joined feature is also characterized. The joined feature is categorized into a first conductive mask, the cut shape is categorized into a cut mask, and a third feature is categorized into a second conductive mask. The categorized shapes and features of the first conductive mask, the second conductive mask, and the cut mask are provided for manufacturing a mask set corresponding to the categorized shapes and features.Type: GrantFiled: April 20, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Hsiang Lung, Kuei-Shun Chen, Meng-Wei Chen, Chia-Ying Lee
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Publication number: 20130280909Abstract: A method for optimizing masks used for forming conductive features and a method for creating the mask features on an IC device are disclosed. An exemplary embodiment includes receiving a design database including a plurality of conductive features. First and second features suitable for joining are identified from the plurality of conductive features. A joined feature corresponding to the first and the second features is characterized. A cut shape configured to separate the first and second features from the joined feature is also characterized. The joined feature is categorized into a first conductive mask, the cut shape is categorized into a cut mask, and a third feature is categorized into a second conductive mask. The categorized shapes and features of the first conductive mask, the second conductive mask, and the cut mask are provided for manufacturing a mask set corresponding to the categorized shapes and features.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Hsiang Lung, Kuei-Shun Chen, Meng-Wei Chen, Chia-Ying Lee