Patents by Inventor Yuan-Hsun Chang
Yuan-Hsun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240190701Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.Type: ApplicationFiled: November 18, 2023Publication date: June 13, 2024Inventors: Chien-Wei CHANG, Ya-Jen SHEUH, Ren-Dou LEE, Yi-Chih CHANG, Yi-Hsun CHIU, Yuan-Hsin CHI
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Patent number: 10574431Abstract: A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.Type: GrantFiled: January 30, 2019Date of Patent: February 25, 2020Assignee: M31 Technology CorporationInventors: Ching-Hsiang Chang, Yuan-Hsun Chang, Yueh-Chuan Lu, Huai-Te Wang
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Publication number: 20190165925Abstract: A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.Type: ApplicationFiled: January 30, 2019Publication date: May 30, 2019Inventors: Ching-Hsiang Chang, Yuan-Hsun Chang, Yueh-Chuan Lu, Huai-Te Wang
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Patent number: 10263762Abstract: The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).Type: GrantFiled: July 19, 2018Date of Patent: April 16, 2019Assignee: M31 Technology CorporationInventors: Ching-Hsiang Chang, Yuan-Hsun Chang, Yueh-Chuan Lu, Huai-Te Wang
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Integrated circuit with clock detection and selection function and related method and storage device
Patent number: 10256801Abstract: An integrated circuit with clock detection and selection function for use in a storage device includes: an embedded oscillator, a detection circuit and a selection circuit. The embedded oscillator is configured to generate an embedded clock signal. The detection circuit includes a sampling and counting circuit and a clock determination circuit. The detection circuit, and is configured to detect existence of a reference clock signal provided by a host based on sampling and counting operations that are performed according to a signal on a clock signal lane and the embedded clock signal. The selection circuit is coupled to the detection circuit and the embedded oscillator, and is configured to select one of the embedded clock signal and the signal on the clock signal lane according to the existence of the reference clock signal as an output clock signal, thereby to provide the output clock signal to the storage device.Type: GrantFiled: July 19, 2017Date of Patent: April 9, 2019Assignee: M31 Technology CorporationInventors: Chih-Cheng Hsu, Yuan-Hsun Chang, Chang-Huan Liang -
Publication number: 20180323952Abstract: The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).Type: ApplicationFiled: July 19, 2018Publication date: November 8, 2018Inventors: Ching-Hsiang Chang, Yuan-Hsun Chang, Yueh-Chuan Lu, Huai-Te Wang
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INTEGRATED CIRCUIT WITH CLOCK DETECTION AND SELECTION FUNCTION AND RELATED METHOD AND STORAGE DEVICE
Publication number: 20180059159Abstract: An integrated circuit with clock detection and selection function for use in a storage device includes: an embedded oscillator, a detection circuit and a selection circuit. The embedded oscillator is configured to generate an embedded clock signal. The detection circuit includes a sampling and counting circuit and a clock determination circuit. The detection circuit, and is configured to detect existence of a reference clock signal provided by a host based on sampling and counting operations that are performed according to a signal on a clock signal lane and the embedded clock signal. The selection circuit is coupled to the detection circuit and the embedded oscillator, and is configured to select one of the embedded clock signal and the signal on the clock signal lane according to the existence of the reference clock signal as an output clock signal, thereby to provide the output clock signal to the storage device.Type: ApplicationFiled: July 19, 2017Publication date: March 1, 2018Inventors: Chih-Cheng Hsu, Yuan-Hsun Chang, Chang-Huan Liang -
Patent number: 9025713Abstract: A method for a first electronic device processing data based on information from a second electronic device may comprise: receiving a first signal from the second electronic device; extracting a first clock based on the first signal; adjusting an oscillator based on the first clock so as to generate a second clock; and selecting one from the first and second clocks. In an embodiment of the present invention, the first electronic device may be configured to be hot plugged into the second electronic device. The method may further comprise processing a data stream from the second electronic device based on said selecting said one from the first and second clocks. The method may further comprise transmitting a data stream to the second electronic device based on said selecting said one from the first and second clocks.Type: GrantFiled: October 4, 2013Date of Patent: May 5, 2015Assignee: M31 Technology CorporationInventors: Yu-Sheng Yi, Ting-Chun Huang, Yuan-Hsun Chang
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Publication number: 20150098542Abstract: A method for a first electronic device processing data based on information from a second electronic device may comprise: receiving a first signal from the second electronic device; extracting a first clock based on the first signal; adjusting an oscillator based on the first clock so as to generate a second clock; and selecting one from the first and second clocks. In an embodiment of the present invention, the first electronic device may be configured to be hot plugged into the second electronic device. The method may further comprise processing a data stream from the second electronic device based on said selecting said one from the first and second clocks. The method may further comprise transmitting a data stream to the second electronic device based on said selecting said one from the first and second clocks.Type: ApplicationFiled: October 4, 2013Publication date: April 9, 2015Applicant: M31 Technology CorporationInventors: Yu-Sheng Yi, Ting-Chun Huang, Yuan-Hsun Chang
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Patent number: 8917133Abstract: The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.Type: GrantFiled: October 21, 2013Date of Patent: December 23, 2014Assignee: M31 Technology CorporationInventors: Chih-Jou Lin, Yuan-Hsun Chang, Cheng-Ji Chang, Ting-Chun Huang, Yu-Sheng Yi
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Publication number: 20140043082Abstract: The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.Type: ApplicationFiled: October 21, 2013Publication date: February 13, 2014Applicant: M31 Technology CorporationInventors: Chih-Jou Lin, Yuan-Hsun Chang, Cheng-Ji Chang, Ting-Chun Huang, Yu-Sheng Yi
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Patent number: 8593199Abstract: The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.Type: GrantFiled: May 21, 2012Date of Patent: November 26, 2013Assignee: M31 Technology CorporationInventors: Chih-Jou Lin, Yuan-Hsun Chang, Cheng-Ji Chang
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Publication number: 20130271198Abstract: The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.Type: ApplicationFiled: May 21, 2012Publication date: October 17, 2013Inventors: CHIH-JOU LIN, YUAN-HSUN CHANG, CHENG-JI CHANG
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Patent number: 7944194Abstract: A reference current generator circuit suitable for low-voltage applications is provided. The generator circuit is fabricated in a chip for generating a precise reference current based on a precise reference voltage and a precise external resistor. The generator circuit provides an equivalent resistance coupled in parallel with the external resistor to provide resistance compensation and reduce the impedance of seeing into the chip from a chip pad. In addition to the resistance compensation, only moderate capacitance compensation is required to enhance the phase margin of the generator circuit, so as to achieve a stable loop. Therefore, chip area and cost can be reduced in low-voltage applications. In addition, the generator circuit reproduces the reference current generated by the external resistor by utilizing current mirrors, so as to eliminate the effect on currents caused by parallel coupling of the equivalent resistance and the external resistor.Type: GrantFiled: December 1, 2008Date of Patent: May 17, 2011Assignee: Faraday Technology Corp.Inventors: Ting-Chun Huang, Kuan-Yu Chen, Yuan-Hsun Chang
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Patent number: 7880534Abstract: A reference circuit for providing a precision voltage and a precision current includes a bandgap voltage reference circuit, a positive temperature coefficient calibrating circuit, a threshold voltage superposing circuit and precision current generator interconnected in cascade. From the bandgap voltage reference circuit, a bandgap voltage is outputted as the precision voltage, and a PTAT current is outputted to the positive temperature coefficient calibrating circuit along with the bandgap voltage for generating a PTAT voltage. In response to the PTAT voltage from the positive temperature coefficient calibrating circuit, the threshold voltage superposing circuit generates a first voltage which is equal to the PTAT voltage plus a threshold voltage. Then the precision current generator outputs a reference current as the precision current in response to the first voltage.Type: GrantFiled: May 8, 2009Date of Patent: February 1, 2011Assignee: Faraday Technology Corp.Inventors: Din-Jiun Huang, Kuan-Yu Chen, Yuan-Hsun Chang
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Patent number: 7830181Abstract: A deglitch circuit including signal transmission units is provided. The signal transmission units are connected in serial to form a signal transmission unit string, and a first signal transmission unit of the signal transmission unit string receives a digital signal. Each signal transmission unit includes a first switch, a first delay circuit and a second switch. First and second terminals of the first switch are coupled to a previous signal transmission unit of the signal transmission unit string and an input terminal of the first delay circuit, respectively. The second switch is coupled between an output terminal of the first delay circuit and a first voltage. When the digital signal has a first logic state, the first switch is turned off, and the second switch is turned on. When the digital signal has a second logic state, the first switch is turned on, and the second switch is turned off.Type: GrantFiled: September 8, 2009Date of Patent: November 9, 2010Assignee: Faraday Technology Corp.Inventors: Ting-Chun Huang, Kuan-Yu Chen, Yuan-Hsun Chang
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Publication number: 20100060345Abstract: A reference circuit for providing a precision voltage and a precision current includes a bandgap voltage reference circuit, a positive temperature coefficient calibrating circuit, a threshold voltage superposing circuit and precision current generator interconnected in cascade. From the bandgap voltage reference circuit, a bandgap voltage is outputted as the precision voltage, and a PTAT current is outputted to the positive temperature coefficient calibrating circuit along with the bandgap voltage for generating a PTAT voltage. In response to the PTAT voltage from the positive temperature coefficient calibrating circuit, the threshold voltage superposing circuit generates a first voltage which is equal to the PTAT voltage plus a threshold voltage. Then the precision current generator outputs a reference current as the precision current in response to the first voltage.Type: ApplicationFiled: May 8, 2009Publication date: March 11, 2010Applicant: FARADAY TECHNOLOGY CORPORATIONInventors: Din-Jiun Huang, Kuan-Yu Chen, Yuan-Hsun Chang
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Publication number: 20100052645Abstract: A reference current generator circuit suitable for low-voltage applications is provided. The generator circuit is fabricated in a chip for generating a precise reference current based on a precise reference voltage and a precise external resistor. The generator circuit provides an equivalent resistance coupled in parallel with the external resistor to provide resistance compensation and reduce the impedance of seeing into the chip from a chip pad. In addition to the resistance compensation, only moderate capacitance compensation is required to enhance the phase margin of the generator circuit, so as to achieve a stable loop. Therefore, chip area and cost can be reduced in low-voltage applications. In addition, the generator circuit reproduces the reference current generated by the external resistor by utilizing current mirrors, so as to eliminate the effect on currents caused by parallel coupling of the equivalent resistance and the external resistor.Type: ApplicationFiled: December 1, 2008Publication date: March 4, 2010Applicant: FARADAY TECHNOLOGY CORP.Inventors: Ting-Chun Huang, Kuan-Yu Chen, Yuan-Hsun Chang
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Patent number: 7282902Abstract: A voltage regulator apparatus, wherein two transistors are coupled to an output terminal of a voltage regulator, so as to improve the transient response of output voltage and increase the stability of the output voltage. Besides, it avoids the use of an external capacitor.Type: GrantFiled: March 7, 2004Date of Patent: October 16, 2007Assignee: Faraday Technology Corp.Inventors: Yuan-Hsun Chang, Jia-Jio Huang, Cheng-Chung Chou
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Publication number: 20050194953Abstract: A voltage regulator apparatus, wherein two transistors are coupled to an output terminal of a voltage regulator, so as to improve the transient response of output voltage and increase the stability of the output voltage. Besides, it avoids the use of an external capacitor.Type: ApplicationFiled: March 7, 2004Publication date: September 8, 2005Inventors: YUAN-HSUN CHANG, JIA-JIO HUANG, CHENG-CHUNG CHOU