Patents by Inventor Yuan-Jen Lee
Yuan-Jen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11956971Abstract: A fabrication process for an STT MTJ MRAM device includes steps of cooling the device at individual or at multiple stages in its fabrication. The cooling process, which may be equally well applied during the fabrication of other multi-layered devices, is demonstrated to produce an operational device that is more resistant to adverse thermal effects during operation that would normally cause a similar device not so fabricated to lose stored data and otherwise fail to operate properly.Type: GrantFiled: September 21, 2020Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huanlong Liu, Guenole Jan, Ru-Ying Tong, Jian Zhu, Yuan-Jen Lee, Jodi Mari Iwata, Sahil Patel, Vignesh Sundar
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Publication number: 20240096818Abstract: Devices and method for forming a shielding assembly including a first chip package structure sensitive to magnetic interference (MI), a second chip package structure sensitive to electromagnetic interference (EMI), and a shield surrounding sidewalls and top surfaces of the first chip package structure and the second chip package structure, in which the shield is a magnetic shielding material. In some embodiments, the shield may include silicon steel, in some embodiments, the shield may include Mu-metal. The silicon-steel-based or Mu-metal-based shield may provide both EMI and MI protection to multiple chip package structures with various susceptibilities to EMI and MI.Type: ApplicationFiled: April 20, 2023Publication date: March 21, 2024Inventors: Harry-Hak-Lay Chuang, Yuan-Jen Lee, Kuo-An Liu, Ching-Huang Wang, C.T. Kuo, Tien-Wei Chiang
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Publication number: 20230345842Abstract: A memory device includes a memory unit and a shielding element disposed on the memory unit. The memory unit includes a bottom electrode, a memory element disposed on the bottom electrode, and a top electrode disposed on the memory element. The shielding element is disposed on the memory unit to deviate an external magnetic field away from the memory element.Type: ApplicationFiled: April 22, 2022Publication date: October 26, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Cho WANG, Sheng-Huang HUANG, Yuan-Jen LEE, Jiunyu TSAI, Keng-Ming KUO, Jun-Yao CHEN, Harry-Hak-Lay CHUANG
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Publication number: 20230299010Abstract: In an embodiment, a method includes: receiving a first wafer and a second wafer, the first wafer including a first alignment mark, the first alignment mark including a first grid of first magnetic features, the second wafer including a second alignment mark, the second alignment mark including a second grid of second magnetic features; aligning the first alignment mark with the second alignment mark in an optical alignment process; after the optical alignment process, aligning the first alignment mark with the second alignment mark in a magnetic alignment process, north poles of the first magnetic features being aligned with south poles of the second magnetic features, south poles of the first magnetic features being aligned with north poles of the second magnetic features; and forming bonds between the first wafer and the second wafer.Type: ApplicationFiled: May 19, 2022Publication date: September 21, 2023Inventors: Harry-Haklay Chuang, Yuan-Jen Lee, Nuo Xu, Fang-Lan Chu, Wei Cheng Wu
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Publication number: 20230299041Abstract: In an embodiment, a structure includes: a first device including a first dielectric layer and a first alignment mark in the first dielectric layer, the first alignment mark including a first magnetic cross, the first magnetic cross having a first north pole and a first south pole; and a second device including a second dielectric layer and a second alignment mark in the second dielectric layer, the second alignment mark including a second magnetic cross, the second magnetic cross having a second north pole and a second south pole, the first north pole aligned with the second south pole, the first south pole aligned with the second north pole, the first dielectric layer bonded to the second dielectric layer by dielectric-to-dielectric bonds, the first alignment mark bonded to the second alignment mark by metal-to-metal bonds.Type: ApplicationFiled: May 19, 2022Publication date: September 21, 2023Inventors: Harry-Haklay Chuang, Yuan-Jen Lee, Fang-Lan Chu, Wei Cheng Wu, Nuo Xu
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Publication number: 20230207045Abstract: A magnetoresistive random access memory (MRAM) device is provided. The MRAM device includes a main magnetic tunnel junction (MTJ) array comprising a plurality of memory cells configured to store memory data and a reference MTJ array comprising a plurality of reference cells having MTJ structures. The MRAM device further includes a controller operatively associated with the main MTJ array and the reference MTJ array. The controller is configured to receive a gross resistance of the reference MTJ array being related to a strength of an external magnetic field, determine whether the external magnetic field is fatal based on the received gross resistance of the reference MTJ array and a pre-determined threshold, and provide notification indicating that the memory data stored in the main MTJ array is untrustworthy if it is determined that the external magnetic field around the MRAM device is fatal.Type: ApplicationFiled: April 20, 2022Publication date: June 29, 2023Inventors: Harry-Hak-Lay Chuang, Yuan-Jen Lee, Tien-Wei Chiang, Yi-Chun Shih
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Publication number: 20230065850Abstract: An integrated circuit device includes a substrate, a memory cell, a magnetic shielding element, an interlayer dielectric layer, and a metallization pattern. The memory cell is over the substrate. The memory cell includes a bottom electrode, a resistance switching element over the bottom electrode, a top electrode over the resistance switching element. The magnetic shielding element is around the memory cell. The interlayer dielectric layer surrounds the memory cell and the magnetic shielding element. The metallization pattern is in the interlayer dielectric layer and connected to the top electrode.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Jen LEE, Harry-Hak-Lay CHUANG, Tien-Wei CHIANG, Hung Cho WANG, Kuei-Hung SHEN, Sheng-Huang HUANG
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Patent number: 11573270Abstract: A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.Type: GrantFiled: July 1, 2021Date of Patent: February 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guenole Jan, Huanlong Liu, Jian Zhu, Yuan-Jen Lee, Po-Kang Wang
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Patent number: 11569441Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer interfaces with a tunnel barrier and has a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or an oxide or nitride of Ru, Ta, Ti, or Si, wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing thereby promoting BCC structure growth in the oxide layer that results in enhanced free layer PMA and improved thermal stability.Type: GrantFiled: May 18, 2020Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Luc Thomas, Po-Kang Wang, Ru-Ying Tong, Jodi Iwata
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Patent number: 11563170Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30X that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.Type: GrantFiled: December 27, 2019Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian Zhu, Guenole Jan, Yuan-Jen Lee, Huanlong Liu, Ru-Ying Tong, Po-Kang Wang
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Publication number: 20220344578Abstract: A package structure includes an integrated circuit package and a magnetic shielding structure. The integrated circuit package includes a semiconductor chip. The magnetic shielding structure surrounds the integrated circuit package, in which the magnetic shielding structure including a top plate and a bottom plate disposed on two opposite sides of the integrated circuit package.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry-Hak-Lay CHUANG, Yuan-Jen LEE, Tien-Wei CHIANG
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Publication number: 20220246841Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a metal oxide (Mox) layer and a tunnel barrier layer to produce interfacial perpendicular magnetic anisotropy (PMA). The Mox layer has a non-stoichiometric oxidation state to minimize parasitic resistance, and comprises a dopant to fill vacant lattice sites thereby blocking oxygen diffusion through the Mox layer to preserve interfacial PMA and high thermal stability at process temperatures up to 400° C. Various methods of forming the doped Mox layer include deposition of the M layer in a reactive environment of 02 and dopant species in gas form, exposing a metal oxide layer to dopant species in gas form, and ion implanting the dopant. In another embodiment, where the dopant is N, a metal nitride layer is formed on a metal oxide layer, and then an anneal step drives nitrogen into vacant sites in the metal oxide lattice.Type: ApplicationFiled: April 25, 2022Publication date: August 4, 2022Inventors: Guenole Jan, Jodi Mari Iwata, Ru-Ying Tong, Huanlong Liu, Yuan-Jen Lee, Jian Zhu
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Publication number: 20220238798Abstract: A magnetic tunnel junction is disclosed wherein the reference layer and free layer each comprise one layer having a boron content from 25 to 50 atomic %, and an adjoining second layer with a boron content from 1 to 20 atomic %. One of the first and second layers in each of the free layer and reference layer contacts the tunnel barrier. Each boron containing layer has a thickness of 1 to 10 Angstroms and may include one or more B layers and one or more Co, Fe, CoFe, or CoFeB layers. As a result, migration of non-magnetic metals along crystalline boundaries to the tunnel barrier is prevented, and the MTJ has a low defect count of around 10 ppm while maintaining an acceptable TMR ratio following annealing to temperatures of about 400° C. The boron containing layers are selected from CoB, FeB, CoFeB and alloys thereof including CoFeNiB.Type: ApplicationFiled: April 18, 2022Publication date: July 28, 2022Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Po-Kang Wang
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Patent number: 11316098Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a metal oxide (Mox) layer and a tunnel barrier layer to produce interfacial perpendicular magnetic anisotropy (PMA). The Mox layer has a non-stoichiometric oxidation state to minimize parasitic resistance, and comprises a dopant to fill vacant lattice sites thereby blocking oxygen diffusion through the Mox layer to preserve interfacial PMA and high thermal stability at process temperatures up to 400° C. Various methods of forming the doped Mox layer include deposition of the M layer in a reactive environment of O2 and dopant species in gas form, exposing a metal oxide layer to dopant species in gas form, and ion implanting the dopant. In another embodiment, where the dopant is N, a metal nitride layer is formed on a metal oxide layer, and then an anneal step drives nitrogen into vacant sites in the metal oxide lattice.Type: GrantFiled: December 27, 2019Date of Patent: April 26, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guenole Jan, Jodi Mari Iwata, Ru-Ying Tong, Huanlong Lui, Yuan-Jen Lee, Jian Zhu
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Patent number: 11309489Abstract: A magnetic tunnel junction is disclosed wherein the reference layer and free layer each comprise one layer having a boron content from 25 to 50 atomic %, and an adjoining second layer with a boron content from 1 to 20 atomic %. One of the first and second layers in each of the free layer and reference layer contacts the tunnel barrier. Each boron containing layer has a thickness of 1 to 10 Angstroms and may include one or more B layers and one or more Co, Fe, CoFe, or CoFeB layers. As a result, migration of non-magnetic metals along crystalline boundaries to the tunnel barrier is prevented, and the MTJ has a low defect count of around 10 ppm while maintaining an acceptable TMR ratio following annealing to temperatures of about 400° C. The boron containing layers are selected from CoB, FeB, CoFeB and alloys thereof including CoFeNiB.Type: GrantFiled: August 31, 2020Date of Patent: April 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huanlong Liu, Yuan-Jen Lee, Jian Zhu, Guenole Jan, Po-Kang Wang
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Publication number: 20210325460Abstract: A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.Type: ApplicationFiled: July 1, 2021Publication date: October 21, 2021Inventors: Guenole Jan, Huanlong Liu, Jian Zhu, Yuan-Jen Lee, Po-Kang Wang
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Publication number: 20210210680Abstract: A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a boron containing free layer (FL) is subjected to a plasma treatment with inert gas, and a natural oxidation (NOX) process to form B2O3 before overlying layers are deposited. A metal layer such as Mg is deposited on the FL as a first step in forming a Hk enhancing layer that increases FL perpendicular magnetic anisotropy, or as a first step in forming a tunnel barrier layer on the FL. One or more anneal steps are essential in assisting B2O3 segregation from the free layer and thereby increasing the FL magnetic moment. A post-oxidation plasma treatment may also be used to partially remove B2O3 proximate to the FL top surface before the metal layer is deposited. Both plasma treatments use low power (<50 Watts) to remove a maximum of 2 Angstroms FL thickness.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Inventors: Guenole Jan, Jodi Mari Iwata, Ru-Ying Tong, Huanlong Liu, Yuan-Jen Lee, Jian Zhu
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Patent number: 11054471Abstract: A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.Type: GrantFiled: December 16, 2019Date of Patent: July 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guenole Jan, Huanlong Liu, Jian Zhu, Yuan-Jen Lee, Po-Kang Wang
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Patent number: 10978124Abstract: Circuits and methods for programming a MTJ stack of an MRAM cell minimizes a ferromagnetic free layer or pinned layer polarization reversal due to back-hopping. The programming begins by applying a first segment of the segment of the write pulse at a first write voltage level for a first time period to program the MTJ stack. A second segment of the segment of the write pulse at a second write voltage level that is less than the first write voltage level is applied to the magnetic tunnel junction stack for a second time period to correct the polarization of the MTJ when the MTJ stack has reversed polarization during the first time period. The second segment of the segment of the write pulse may be a ramp, or multiple ramps, or have a quiescent period between it and the first segment of the write pulse.Type: GrantFiled: June 29, 2020Date of Patent: April 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huanlong Liu, Guenole Jan, Yuan-Jen Lee, Jian Zhu, Po-Kang Wang
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Patent number: 10957851Abstract: A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a boron containing free layer (FL) is subjected to a plasma treatment with inert gas, and a natural oxidation (NOX) process to form B2O3 before overlying layers are deposited. A metal layer such as Mg is deposited on the FL as a first step in forming a Hk enhancing layer that increases FL perpendicular magnetic anisotropy, or as a first step in forming a tunnel barrier layer on the FL. One or more anneal steps are essential in assisting B2O3 segregation from the free layer and thereby increasing the FL magnetic moment. A post-oxidation plasma treatment may also be used to partially remove B2O3 proximate to the FL top surface before the metal layer is deposited. Both plasma treatments use low power (<50 Watts) to remove a maximum of 2 Angstroms FL thickness.Type: GrantFiled: December 27, 2019Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guenole Jan, Jodi Mari Iwata, Ru-Ying Tong, Huanlong Liu, Yuan-Jen Lee, Jian Zhu