Patents by Inventor Yuan-Kai Chu
Yuan-Kai Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8493260Abstract: A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.Type: GrantFiled: September 22, 2011Date of Patent: July 23, 2013Assignee: Himax Technologies LimitedInventors: Yuan-Kai Chu, Jin-Fu Lin
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Publication number: 20130076554Abstract: A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.Type: ApplicationFiled: September 22, 2011Publication date: March 28, 2013Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: YUAN-KAI CHU, Jin-Fu LIN
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Publication number: 20110095737Abstract: A voltage regulator and an integrated circuit using the voltage regulator is provided. The voltage regulator has a bandgap reference circuit, an operational amplifier, a power transistor and a voltage divider. The bandgap reference circuit generates a bandgap reference voltage. The operational amplifier receives the bandgap reference voltage and a feedback voltage to output a control signal for the power transistor. The power transistor is powered by a first voltage source and transforms the first voltage source to a second voltage source according to the control signal. The second voltage source is divided by the voltage divider to generate the feedback voltage and is further used in powering the bandgap reference circuit and the operational amplifier.Type: ApplicationFiled: October 27, 2009Publication date: April 28, 2011Applicants: HIMAX TECHNOLOGIES LIMITED, HIMAX MEDIA SOLUTIONS, INC.Inventors: Yuan-Kai Chu, Hui-Min Wang
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Patent number: 7663410Abstract: A current-mode differential transmitter, receiving a single-end input voltage signal and accordingly generating a differential output current signal, is provided. The transmitter includes a first switch, a second switch and a current mirror. The first switch is coupled in a first current path and controlled by the single-end input voltage signal. The second switch is coupled in a second current path and controlled by an inverted signal of the single-end input voltage signal. The current mirror mirrors a reference current to the first current path when the first switch is turned on, and mirrors the reference current to the second current path when the second switch is turned on. The differential output current signal is derived from the currents on the first and second current paths.Type: GrantFiled: October 4, 2007Date of Patent: February 16, 2010Assignee: Himax Technologies LimitedInventors: Chih-Haur Huang, Yuan-Kai Chu
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Patent number: 7560969Abstract: A receiver of a high speed digital interface includes at least one differential amplifier, a pair of resistive elements, a current source and a pair of transistors. The differential amplifier receives a small differential signal at a pair of input terminals and outputs an amplified differential signal. Each of the resistive elements has one end coupled to one of the input terminals of the differential amplifier and the other end receiving a reference voltage. The pair of transistors has drains respectively coupled to the input terminals of the differential amplifier, sources commonly coupled to the current source and gates receiving a differential feedback signal derived from the amplified differential signal.Type: GrantFiled: September 10, 2007Date of Patent: July 14, 2009Assignee: Himax Technologies LimitedInventor: Yuan-Kai Chu
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Publication number: 20090091356Abstract: A current-mode differential transmitter, receiving a single-end input voltage signal and accordingly generating a differential output current signal, is provided. The transmitter includes a first switch, a second switch and a current mirror. The first switch is coupled in a first current path and controlled by the single-end input voltage signal. The second switch is coupled in a second current path and controlled by an inverted signal of the single-end input voltage signal. The current mirror mirrors a reference current to the first current path when the first switch is turned on, and mirrors the reference current to the second current path when the second switch is turned on. The differential output current signal is derived from the currents on the first and second current paths.Type: ApplicationFiled: October 4, 2007Publication date: April 9, 2009Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Chih-Haur Huang, Yuan-Kai Chu
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Publication number: 20090067545Abstract: A receiver of a high speed digital interface includes at least one differential amplifier, a pair of resistive elements, a current source and a pair of transistors. The differential amplifier receives a small differential signal at a pair of input terminals and outputs an amplified differential signal. Each of the resistive elements has one end coupled to one of the input terminals of the differential amplifier and the other end receiving a reference voltage. The pair of transistors has drains respectively coupled to the input terminals of the differential amplifier, sources commonly coupled to the current source and gates receiving a differential feedback signal derived from the amplified differential signal.Type: ApplicationFiled: September 10, 2007Publication date: March 12, 2009Applicant: HIMAX TECHNOLOGIES LIMITEDInventor: Yuan-Kai Chu
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Patent number: 7495514Abstract: A low noise amplifier including a first-stage signal amplifier, a second-stage signal amplifier and a gain control unit is disclosed. The first-stage signal amplifier is for receiving an input signal and outputting a first output signal accordingly. The second-stage signal amplifier is coupled to the first-stage signal amplifier for outputting a second output signal according to the first output signal. The second-stage signal amplifier includes a first output transistor for outputting the second output signal. The gain control unit includes a first variable resistance device coupled to an input terminal of the first output transistor for adjusting voltage gain of the second output signal.Type: GrantFiled: February 17, 2006Date of Patent: February 24, 2009Assignees: Himax Technologies Limited, NCKU Research and Development FoundationInventors: Da-Rong Huang, Huey-Ru Chuang, Yuan-Kai Chu
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Patent number: 7375741Abstract: A circuit and a method for eliminating interference introduced from an image channel into a desired channel is described. The circuit includes a splitter and an adder. The splitter generates signals split from a received signal having frequency components within the desired and image channel. The adder adds together the signals output from the splitter. The circuit can be used in an TV tuner.Type: GrantFiled: March 24, 2005Date of Patent: May 20, 2008Assignee: Himax Technologies LimitedInventors: Jian-Jiang Huang, Yuan-Kai Chu
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Patent number: 7206007Abstract: A method for video processing which provides a scaled image using two different clock frequencies is provided. The method receives source pixel data using a first clock signal and scales the source pixel data to destination pixel data. After that, the destination pixel data is provided using a second clock signal having a second clock frequency and a third clock signal having a third clock frequency during blanking period and active period, respectively.Type: GrantFiled: February 4, 2005Date of Patent: April 17, 2007Assignee: Himax Technologies, Inc.Inventors: Chung-Hsun Huang, Yuan-Kai Chu, Kuei-Hsiang Chen
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Patent number: 7177202Abstract: A method for accessing a single port memory is provided. A single port memory is used as a line buffer and divided into a plurality of memory blocks. The line buffer data is written into or read out from these memory blocks by turns with a special sequence corresponding to the operation mode; for example, a normal mode or a PLM mode. Therefore, the line buffer data can be written into or read out from the line buffer at the same time, and the size and cost of integrated circuit can be reduced.Type: GrantFiled: September 25, 2004Date of Patent: February 13, 2007Assignee: Himax Technologies, Inc.Inventors: Yuan-Kai Chu, Pen-Hsin Chen, Kuei-Hsiang Chen, Lin-Kai Bu
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Publication number: 20060215063Abstract: A circuit and a method for eliminating interference introduced from an image channel into a desired channel is described. The circuit includes a splitter and an adder. The splitter generates signals split from a received signal having frequency components within the desired and image channel. The adder adds together the signals output from the splitter. The circuit can be used in an TV tuner.Type: ApplicationFiled: March 24, 2005Publication date: September 28, 2006Applicant: HIMAX TECHNOLOGIES, INC.Inventors: Jian-Jang Huang, Yuan-Kai Chu
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Publication number: 20060198176Abstract: A low noise amplifier including a first-stage signal amplifier, a second-stage signal amplifier and a gain control unit is disclosed. The first-stage signal amplifier is for receiving an input signal and outputting a first output signal accordingly. The second-stage signal amplifier is coupled to the first-stage signal amplifier for outputting a second output signal according to the first output signal. The second-stage signal amplifier includes a first output transistor for outputting the second output signal. The gain control unit includes a first variable resistance device coupled to an input terminal of the first output transistor for adjusting voltage gain of the second output signal.Type: ApplicationFiled: February 17, 2006Publication date: September 7, 2006Inventors: Da-Rong Huang, Huey-Ru Chuang, Yuan-Kai Chu
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Publication number: 20060176320Abstract: A method for video processing which provides a scaled image using two different clock frequencies is provided. The method receives source pixel data using a first clock signal and scales the source pixel data to destination pixel data. After that, the destination pixel data is provided using a second clock signal having a second clock frequency and a third clock signal having a third clock frequency during blanking period and active period, respectively.Type: ApplicationFiled: February 4, 2005Publication date: August 10, 2006Inventors: Chung-Hsun Huang, Yuan-Kai Chu, Kuei-Hsiang Chen
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Publication number: 20050281124Abstract: A method for accessing a single port memory is provided. A single port memory is used as a line buffer and divided into a plurality of memory blocks. The line buffer data is written into or read out from these memory blocks by turns with a special sequence corresponding to the operation mode; for example, a normal mode or a PLM mode. Therefore, the line buffer data can be written into or read out from the line buffer at the same time, and the size and cost of integrated circuit can be reduced.Type: ApplicationFiled: September 25, 2004Publication date: December 22, 2005Inventors: Yuan-Kai Chu, Pen-Hsin Chen, Kuei-Hsiang Chen, Lin-Kai Bu