Abstract: A heat dissipation base includes a fixing plate and a metal heat conduction block. The fixing plate includes a plurality of heat pipe partitions and a plurality of heat pipe fixing openings, and the heat pipe fixing openings are formed between the heat pipe partitions. The metal heat conduction block is fixed to the fixing plate, and the fixing plate further includes a plurality of supporting portions to support shear surfaces at two ends of the heat conduction block.

Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.

Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.

Abstract: A display device includes a display area, a pixel array, a display medium layer, and a color filter layer. The display area includes a plurality of sub-pixel regions, and each of the sub-pixel regions has a length and a width that are substantially the same. The pixel array corresponds to the display area in position. The display medium layer is located on the pixel array. The color filter layer includes a plurality of color resists. The color resists are arranged along a first direction and a second direction different from the first direction. Two adjacent color resists arranged along the first direction have different colors, two adjacent color resists arranged along the second direction have different colors, and adjacent two of the color resists are spaced apart from each other.

Abstract: A cursor image detection comparison and feedback status determination method is disclosed. The method is based on a non-invasive data-extraction system architecture, and uses an image processing unit to perform detection comparison on a cursor image shown on an operation screen outputted from a machine controller. The method includes steps of obtaining cursor foreground and background images set by a user, and selecting an algorithm to process the cursor foreground and background images to generate a cursor mask, and reading a cursor image and applying the cursor mask on the cursor image for pattern comparison, transmitting information of a comparison result and a cursor feedback status to a software control system, so as to provide a correction system to perform a cursor process program and check whether the movement of the cursor meet a position controlled by a feedback and correction system, thereby completing closed-loop control for the cursor.

Abstract: A modified alloy powder includes a powdered alloy; and a carbide powder, mixed in the powdered alloy; wherein the carbide powder has a particle size smaller than that of the powdered alloy, and the carbide powder is dedicated to powder bed selective laser melting and laser metal deposition technology. Being used as a grain refiner and a grain growth inhibitor, the effect of refinement in the grain size of final products and improvement of the workpiece strength can be achieved.

Abstract: A mobile device includes a metal back cover, an edge appearance element, a display device, a supporting element, an antenna structure, and a ground element. The edge appearance element is made of a nonconductive material. The edge appearance element is connected to the metal back cover. The display device is disposed opposite to the metal back cover. The antenna structure is disposed on the supporting element. The antenna structure is positioned between the edge appearance element and the display device. The ground element is coupled to the metal back cover. The electromagnetic waves of the antenna structure are transmitted through the edge appearance element, such that the mobile device supports wireless communication.

Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

Abstract: A memory device that includes a driver IC, a voltage-dividing resistor, at least two noise-suppressing resistors and at least three memory ICs is provided. A terminal of the voltage-dividing resistor is electrically coupled to a voltage source and another other terminal of the voltage-dividing resistor is electrically coupled to the driver IC through an end a connection path. One of the memory ICs is electrically coupled to the voltage-dividing resistor and the driver IC through the end the connection path. Each of at least two of the other memory ICs is electrically coupled to the connection path through one of the noise-suppressing resistors and is further electrically coupled to the driver IC.

Abstract: A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.

Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.

Abstract: A liquid crystal composition includes at least one of a monofunctional compound represented by Formula (1) defined herein and a monofunctional compound represented by Formula (2) defined herein, and at least one of a difunctional compound represented by Formula (3) defined herein and a multifunctional compound represented by Formula (4) defined herein.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A cursor image detection comparison and feedback status determination method is disclosed. The method is based on a non-invasive data-extraction system architecture, and uses an image processing unit to perform detection comparison on a cursor image shown on an operation screen outputted from a machine controller. The method includes steps of obtaining cursor foreground and background images set by a user, and selecting an algorithm to process the cursor foreground and background images to generate a cursor mask, and reading a cursor image and applying the cursor mask on the cursor image for pattern comparison, transmitting information of a comparison result and a cursor feedback status to a software control system, so as to provide a correction system to perform a cursor process program and check whether the movement of the cursor meet a position controlled by a feedback and correction system, thereby completing closed-loop control for the cursor.

Abstract: An electrophoretic display apparatus including a driving array substrate, a color filter layer, and an electrophoretic display film is provided. The driving array substrate has a plurality of display units. The color filter layer is disposed on the driving array substrate. The color filter layer includes a plurality of color filter patterns. Each of the display units corresponds to the color filter patterns of two different colors. The electrophoretic display film is between the driving array substrate and the color filter layer. The electrophoretic display film includes a plurality of display mediums. Each of the display mediums includes an electrophoretic liquid, a plurality of color charged particles, a plurality of black charged particles, and a plurality of white charged particles. A color of the color charged particles is different from colors of the color filter patterns.

Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.

Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.

Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.