Patents by Inventor Yuan-Long Siao
Yuan-Long Siao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10281942Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: GrantFiled: February 26, 2018Date of Patent: May 7, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
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Publication number: 20180188756Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: ApplicationFiled: February 26, 2018Publication date: July 5, 2018Inventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
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Patent number: 9910451Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: GrantFiled: February 17, 2014Date of Patent: March 6, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
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Patent number: 9696746Abstract: A band gap reference circuit is provided that includes a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (Ra), a fifth resistor (Rb), a capacitor (Ca), an operational amplifier A, a first field effect transistor (FET) (P1), a second FET (P2), a third FET (P3), a fourth FET (Pa), a first bipolar junction transistor (BJT) (Q1), a second BJT (Q2), and a third BJT (Q3). P3 and Rb are used to control Pa, which is configured to control current flow to a reference node, and thus a reference voltage (Vref) output by the band gap reference circuit. The band gap reference circuit is configured to output a substantially constant reference voltage and is less sensitive or susceptible to noise from a power supply. Additionally, the band gap reference circuit prevents Vref from overshooting when the band gap circuit is enabled.Type: GrantFiled: December 14, 2015Date of Patent: July 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventor: Yuan-Long Siao
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Patent number: 9438103Abstract: The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a NMOS transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected NMOS transistors coupled in series. A first voltage multiplier circuit is configured to generate a first two-phase output signal having a maximum voltage value that is twice the supply voltage. The first two-phase output signal is applied to the gate of the NMOS transistor, forming a conductive channel between the drain and the source, thereby allowing the supply voltage to pass through the NMOS transistor without a threshold voltage drop. Therefore, degradation of the charge pump output voltage due to voltage drops of the NMOS transistor is reduced, resulting in larger output voltages.Type: GrantFiled: January 13, 2015Date of Patent: September 6, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yuan-Long Siao
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Publication number: 20160098056Abstract: A band gap reference circuit is provided that includes a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (Ra), a fifth resistor (Rb), a capacitor (Ca), an operational amplifier A, a first field effect transistor (FET) (P1), a second FET (P2), a third FET (P3), a fourth FET (Pa), a first bipolar junction transistor (BJT) (Q1), a second BJT (Q2), and a third BJT (Q3). P3 and Rb are used to control Pa, which is configured to control current flow to a reference node, and thus a reference voltage (Vref) output by the band gap reference circuit. The band gap reference circuit is configured to output a substantially constant reference voltage and is less sensitive or susceptible to noise from a power supply. Additionally, the band gap reference circuit prevents Vref from overshooting when the band gap circuit is enabled.Type: ApplicationFiled: December 14, 2015Publication date: April 7, 2016Inventor: Yuan-Long Siao
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Patent number: 9213353Abstract: A band gap reference circuit is provided that includes a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (Ra), a fifth resistor (Rb), a capacitor (Ca), an operational amplifier A, a first field effect transistor (FET) (P1), a second FET (P2), a third FET (P3), a fourth FET (Pa), a first bipolar junction transistor (BJT) (Q1), a second BJT (Q2), and a third BJT (Q3). P3 and Rb are used to control Pa, which is configured to control current flow to a reference node, and thus a reference voltage (Vref) output by the band gap reference circuit. The band gap reference circuit is configured to output a substantially constant reference voltage and is less sensitive or susceptible to noise from a power supply. Additionally, the band gap reference circuit prevents Vref from overshooting when the band gap circuit is enabled.Type: GrantFiled: March 13, 2013Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventor: Yuan-Long Siao
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Publication number: 20150234403Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: ApplicationFiled: February 17, 2014Publication date: August 20, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
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Publication number: 20150123727Abstract: The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a NMOS transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected NMOS transistors coupled in series. A first voltage multiplier circuit is configured to generate a first two-phase output signal having a maximum voltage value that is twice the supply voltage. The first two-phase output signal is applied to the gate of the NMOS transistor, forming a conductive channel between the drain and the source, thereby allowing the supply voltage to pass through the NMOS transistor without a threshold voltage drop. Therefore, degradation of the charge pump output voltage due to voltage drops of the NMOS transistor is reduced, resulting in larger output voltages.Type: ApplicationFiled: January 13, 2015Publication date: May 7, 2015Inventor: Yuan-Long Siao
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Patent number: 8963623Abstract: The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a NMOS transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected NMOS transistors coupled in series. A first voltage multiplier circuit is configured to generate a first two-phase output signal having a maximum voltage value that is twice the supply voltage. The first two-phase output signal is applied to the gate of the NMOS transistor, forming a conductive channel between the drain and the source, thereby allowing the supply voltage to pass through the NMOS transistor without a threshold voltage drop. Therefore, degradation of the charge pump output voltage due to voltage drops of the NMOS transistor is reduced, resulting in larger output voltages.Type: GrantFiled: May 29, 2012Date of Patent: February 24, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yuan-Long Siao
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Publication number: 20130320944Abstract: An amplification circuit includes a first amplifier, a second amplifier, and a power supply rejection ratio (PSRR) boost circuit. The first amplifier has an output. The second amplifier has an input coupled to the output of the first amplifier and a power node coupled to a power supply line. The PSRR boost circuit is coupled between the input of the second amplifier and the power supply line, and the PSRR boost circuit comprises a resistance device and a capacitance device connected in series with the resistance device.Type: ApplicationFiled: June 4, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Yuan-Long SIAO
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Publication number: 20130222050Abstract: The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a NMOS transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected NMOS transistors coupled in series. A first voltage multiplier circuit is configured to generate a first two-phase output signal having a maximum voltage value that is twice the supply voltage. The first two-phase output signal is applied to the gate of the NMOS transistor, forming a conductive channel between the drain and the source, thereby allowing the supply voltage to pass through the NMOS transistor without a threshold voltage drop. Therefore, degradation of the charge pump output voltage due to voltage drops of the NMOS transistor is reduced, resulting in larger output voltages.Type: ApplicationFiled: May 29, 2012Publication date: August 29, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yuan-Long Siao
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Patent number: 8503252Abstract: A sense amplifier circuit comprises a first inverter configured to provide a first trigger point during a pre-charge stage of a READ operation of a memory cell and provide a second trigger point either lower or higher than the first trigger point during a sense stage of the READ operation of the memory cell. The sense amplifier circuit further comprises a plurality of inverters coupled between an output of the first inverter and an output of the sense amplifier and a pre-charge device. The sense amplifier circuit having a dynamic trigger point can deliver faster data access time as well as less power consumption.Type: GrantFiled: May 31, 2011Date of Patent: August 6, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yuan-Long Siao
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Patent number: 8339884Abstract: A sense amplifier circuit includes a precharge circuit configured to precharge a bit line coupled to a sensing node in response to a precharge control signal and a sense output circuit. The sense output circuit includes a sense output inverter coupled to the sensing node. The sense output inverter is disabled during bit line precharging and for a period after bit line precharging is complete, and thereafter the sense output inverter is enabled.Type: GrantFiled: January 14, 2011Date of Patent: December 25, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Inc.Inventors: Yi-Cheng Huang, Shang-Hsuan Liu, Yuan-Long Siao
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Publication number: 20120307571Abstract: A sense amplifier circuit comprises a first inverter configured to provide a first trigger point during a pre-charge stage of a READ operation of a memory cell and provide a second trigger point either lower or higher than the first trigger point during a sense stage of the READ operation of the memory cell. The sense amplifier circuit further comprises a plurality of inverters coupled between an output of the first inverter and an output of the sense amplifier and a pre-charge device. The sense amplifier circuit having a dynamic trigger point can deliver faster data access time as well as less power consumption.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yuan-Long Siao
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Publication number: 20120182818Abstract: A sense amplifier circuit includes a precharge circuit configured to precharge a bit line coupled to a sensing node in response to a precharge control signal and a sense output circuit. The sense output circuit includes a sense output inverter coupled to the sensing node. The sense output inverter is disabled during bit line precharging and for a period after bit line precharging is complete, and thereafter the sense output inverter is enabled.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Cheng Huang, Shang-Hsuan Liu, Yuan-Long Siao