Patents by Inventor Yuan-sheng Chu

Yuan-sheng Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8392690
    Abstract: A management method for reducing the utilization rate of random access memory (RAM) while reading data from or writing data to the flash memory is disclosed. A physical memory set is constructed from a plurality of physical memory blocks in the flash memory. A logical set is constructed from a plurality of logical blocks wherein the data stored in the logical set are stored in the physical memory set. Further, the data stored in each of the logical blocks are stored in one number of physical memory blocks. A mapping table is constructed and includes a hash function, a logical set table, a physical memory set table, and a set status table for managing the relationship among the physical memory sets, physical memory blocks, and logical blocks while reading data from or writing data to the flash memory.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: March 5, 2013
    Assignee: Genesys Logic, Inc.
    Inventors: Yuan-sheng Chu, Jen-wei Hsieh, Yuan-hao Chang, Tei-wei Kuo, Cheng-chih Yang
  • Publication number: 20080162793
    Abstract: A management method for reducing the utilization rate of random access memory (RAM) while reading data from or writing data to the flash memory is disclosed. A physical memory set is constructed from a plurality of physical memory blocks in the flash memory. A logical set is constructed from a plurality of logical blocks wherein the data stored in the logical set are stored in the physical memory set. Further, the data stored in each of the logical blocks are stored in one number of physical memory blocks. A mapping table is constructed and includes a hash function, a logical set table, a physical memory set table, and a set status table for managing the relationship among the physical memory sets, physical memory blocks, and logical blocks while reading data from or writing data to the flash memory.
    Type: Application
    Filed: December 20, 2007
    Publication date: July 3, 2008
    Applicant: Genesys Logic, Inc.
    Inventors: Yuan-sheng Chu, Jen-wei Hsieh, Yuan-hao Chang, Tei-wei Kuo, Cheng-chih Yang