Abstract: A homogeneous composite substrate includes a woven cloth and at least one fiber membrane. The woven cloth includes a plurality of first fibers. The fiber membrane is disposed on at least one surface of the woven cloth, and the fiber membrane includes a plurality of second fibers, in which a material of the first fibers and a material of the second fibers are the same, a fiber diameter of each first fiber is larger than or equal to 20 ?m and smaller than or equal to 130 ?m, and a fiber diameter of each second fiber is larger than or equal to 3 ?m and smaller than or equal to 10 ?m.

Abstract: A machine learning model classifies points of interest in a parallel reality game hosted by a server. The server generates training data sets that include verified properties for points of interest. The machine learning model may predict unverified properties for points of interest. Players in the parallel reality game may input properties for the points of interest. The machine learning model use the received properties from players as inputs to the machine learning model to verify unverified properties or generate new properties for the points of interest. The server may classify the points of interest as suitable for particular activities, and the server may use the classifications for future activities within the parallel reality game.

Abstract: A method for cleaning surfaces of a substrate processing chamber includes a) supplying a first gas selected from a group consisting of silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), a hydrocarbon (CxHy where x and y are integers) and molecular chlorine (Cl2), boron trichloride (BCl3), and thionyl chloride (SOCl2); b) striking plasma in the substrate processing chamber to etch the surfaces of the substrate processing chamber; c) extinguishing the plasma and evacuating the substrate processing chamber; d) supplying a second gas including fluorine species; e) striking plasma in the substrate processing chamber to etch the surfaces of the substrate processing chamber; and f) extinguishing the plasma and evacuating the substrate processing chamber.

Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

Abstract: This application provides a folding assembly and a foldable electronic device. The folding assembly is applied to a foldable electronic device, and is configured to carry a flexible display screen. The folding assembly includes a shaft base, a first housing, and a second housing. The first housing and the second housing are respectively disposed on both sides of the shaft base. A door plate swing arm is located above the shaft base and is disposed on each of both sides of a center line of the shaft base, one end of each door plate swing arm is rotatably connected to the shaft base, and the other end of each door plate swing arm is rotatably connected to the first housing or the second housing.

Abstract: The present application relates to the prevention or treatment of symptoms and diseases caused by viral infections, such as acute respiratory distress syndrome (ARDS), sepsis or septic shock associated with SARS-CoV-2 and influenza virus infections. The treatment is based on the use of mesenchymal stem cells (MSCs) genetically engineered to overexpress suitable polypeptides such as angiopoeitin-1 (ANGPT1) and IFN-induced transmembrane (IFITM). The MSC-based therapy may be administered to the lung of the patient by injection into the blood system.

Abstract: A defect detection method includes obtaining a first image corresponding to a first area on an object revealing an apparent defect, the first area bounding the area showing the apparent defect; selecting a detection model according to a size of the first image, the detection model selected being one of a group of three models based on dimensions of image, the image being in one of portrait, landscape, or regular square proportions; detecting and confirming or denying a defect on the first image according to the detection model and outputting a detection result, the use of only three possible AI models reduces the likelihood of mis-determinations. An electronic device and a non-volatile storage medium therein, for performing the above-described method, are also disclosed.

Abstract: A method for classifying failures can determine consumer devices on-line as being repairable or not to be repaired. The method obtains a training set, the set including information as to total failure and information as to repairable failure. First key information in repairable failure and second key information in total failure are obtained. A first TF-IDF value of each first key information and a second TF-IDF value of each second key information are computed. A first feature bank is created based on the first TF-IDF value and a first threshold value, and a second feature bank is created based on the second TF-IDF value and a second threshold. Target failure is classified by the trained classifier. A failure classification is quickly achieved. An electronic device and a computer readable storage medium applying the method are also provided.

Abstract: The present invention discloses a method for producing unidirectional hybrid-braided fabrics, including: preparing a first layer of 0° warps; preparing a second layer of 0° warps to a Nth layer of 0° warps; preparing an auxiliary layer of wefts; preparing binding yarns; laying and hybrid-braiding the materials prepared in steps 1-4 to obtain unidirectional hybrid-braided fabrics; and cutting and winding. The 0° warps and wefts of the invention are made of two or more layers of different fibers that are laid in a single direction and finally hybrid-braided. Therefore, two or more different types of materials can be laid, thereby ensuring the uniform distribution and thickness of the fibers in different areas of the hybrid-braided fabric. The grammage of different 0° warp fiber layers can be adjusted freely in a range of 30-3000 grams/m2, thereby realizing performance and cost designability of a composite material.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

Abstract: The present disclosure provides a detailed description of techniques for implementing a wideband low dropout voltage regulator with power supply rejection boost. More specifically, some embodiments of the present disclosure are directed to a voltage regulator comprising a voltage regulator core powered by a supply voltage and providing a regulated voltage output, and a power supply feed forward injection module delivering an injection signal to the voltage regulator core to effect a power supply rejection of the supply voltage variation from the regulated voltage. In one or more embodiments, the injection signal is determined from the supply voltage variation and a gain factor that is based on various design attributes of the output stage of the voltage regulator core. In one or more embodiments, the power supply feed forward injection module comprises a supply voltage sense circuit, a low pass filter, and one or more selectable transconductance amplifiers.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

Abstract: The present invention discloses a method for producing unidirectional hybrid-braided fabrics, including: preparing a first layer of 0° warps; preparing a second layer of 0° warps to a Nth layer of 0° warps; preparing an auxiliary layer of wefts; preparing binding yarns; laying and hybrid-braiding the materials prepared in steps 1-4 to obtain unidirectional hybrid-braided fabrics; and cutting and winding. The 0° warps and wefts of the invention are made of two or more layers of different fibers that are laid in a single direction and finally hybrid-braided. Therefore, two or more different types of materials can be laid, thereby ensuring the uniform distribution and thickness of the fibers in different areas of the hybrid-braided fabric. The grammage of different 0° warp fiber layers can be adjusted freely in a range of 30-3000 grams/m2, thereby realizing performance and cost designability of a composite material.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

Abstract: The present disclosure provides a detailed description of techniques for implementing a wideband low dropout voltage regulator with power supply rejection boost. More specifically, some embodiments of the present disclosure are directed to a voltage regulator comprising a voltage regulator core powered by a supply voltage and providing a regulated voltage output, and a power supply feed forward injection module delivering an injection signal to the voltage regulator core to effect a power supply rejection of the supply voltage variation from the regulated voltage. In one or more embodiments, the injection signal is determined from the supply voltage variation and a gain factor that is based on various design attributes of the output stage of the voltage regulator core. In one or more embodiments, the power supply feed forward injection module comprises a supply voltage sense circuit, a low pass filter, and one or more selectable transconductance amplifiers.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

Abstract: The present disclosure provides a detailed description of techniques for implementing a wideband low dropout voltage regulator with power supply rejection boost. More specifically, some embodiments of the present disclosure are directed to a voltage regulator comprising a voltage regulator core powered by a supply voltage and providing a regulated voltage output, and a power supply feed forward injection module delivering an injection signal to the voltage regulator core to effect a power supply rejection of the supply voltage variation from the regulated voltage. In one or more embodiments, the injection signal is determined from the supply voltage variation and a gain factor that is based on various design attributes of the output stage of the voltage regulator core. In one or more embodiments, the power supply feed forward injection module comprises a supply voltage sense circuit, a low pass filter, and one or more selectable transconductance amplifiers.