Patents by Inventor Yuan-Ting Lin
Yuan-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240194767Abstract: Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.Type: ApplicationFiled: January 29, 2024Publication date: June 13, 2024Inventors: Jen-Hong Chang, Yuan-Ching Peng, Chung-Ting Ko, Kuo-Yi Chao, Chia-Cheng Chao, You-Ting Lin, Chih-Chung Chang, Yi-Hsiu Liu, Jiun-Ming Kuo, Sung-En Lin
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Publication number: 20240172354Abstract: A neutron capture therapy system and a target material for a particle beam generation apparatus, the heat dissipation performance of a target material might be improved. A neutron capture therapy system includes a neutron generation apparatus and a beam shaping body, the neutron generation apparatus includes an accelerator and a target material, and a charged particle beam generated by means of acceleration of the accelerator acts with the target material to generate a neutron beam. The target material includes an active layer, an anti-foaming layer, a heat dissipation layer and a heat conduction layer, the active layer acts with a charged particle beam to generate a neutron beam; the anti-foaming layer suppresses foaming caused by the charged particle beam; the heat dissipation layer directly and rapidly conducts to the heat conduction layer, heat deposited on the active layer, and discharges by means of a cooling medium.Type: ApplicationFiled: January 16, 2024Publication date: May 23, 2024Inventors: Yuan-hao LIU, Chun-ting Lin
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Publication number: 20240162220Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.Type: ApplicationFiled: December 8, 2022Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Yu Chen, Chun-Hao Lin, Yuan-Ting Chuang, Shou-Wei Hsieh
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Publication number: 20240120376Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first active region extending lengthwise along a first direction and having a first width along a second direction perpendicular to the first direction, a second active region extending lengthwise along the first direction and having a second width along the second direction, and an epitaxial feature sandwiched between the first active region and the second active region along the first direction. The first width is greater than the second width.Type: ApplicationFiled: January 26, 2023Publication date: April 11, 2024Inventors: Po Shao Lin, Jiun-Ming Kuo, Yuan-Ching Peng, You-Ting Lin, Yu Mei Jian
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Patent number: 11916548Abstract: A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, an inverter, and a resistor-capacitor (RC) circuit coupled in series with the inverter between the input terminal and the output terminal. The RC circuit includes an NMOS transistor coupled between an RC circuit output terminal and a reference node, a resistor coupled between the RC circuit output terminal and a power supply node, and a capacitor coupled between the RC circuit output terminal and one of the power supply node or the reference node, and the inverter and the RC circuit are configured to generate an output signal at the output terminal based on the input signal.Type: GrantFiled: December 9, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wan-Yen Lin, Yuan-Ju Chan, Bo-Ting Chen
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Publication number: 20230335669Abstract: A semiconductor device is provided, which includes an active structure, a first semiconductor layer, a second semiconductor layer, an intermediate layer, a transition layer and a contact layer. The active structure has two sides and includes an active region. The first semiconductor layer and the second semiconductor layer respectively located on the two sides of the active structure. The intermediate layer is located between the second semiconductor layer and the active structure. The transition layer is located on the second semiconductor layer. The contact layer is located on the transition layer.Type: ApplicationFiled: June 23, 2023Publication date: October 19, 2023Inventors: Meng-Yang CHEN, Yuan-Ting LIN
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Patent number: 11728456Abstract: A semiconductor device is provided, which includes an active structure and a first semiconductor layer. The active structure includes an active region having a topmost surface and a bottommost surface, and a first dopant distributing from the topmost surface to the bottommost surface. The first semiconductor layer is located under the active structure and includes a second dopant. The active region includes a semiconductor material including As.Type: GrantFiled: May 20, 2022Date of Patent: August 15, 2023Assignee: EPISTAR CORPORATIONInventors: Meng-Yang Chen, Yuan-Ting Lin
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Publication number: 20220285576Abstract: A semiconductor device is provided, which includes an active structure and a first semiconductor layer. The active structure includes an active region having a topmost surface and a bottommost surface, and a first dopant distributing from the topmost surface to the bottommost surface. The first semiconductor layer is located under the active structure and includes a second dopant. The active region includes a semiconductor material including As.Type: ApplicationFiled: May 20, 2022Publication date: September 8, 2022Inventors: Meng-Yang CHEN, Yuan-Ting LIN
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Patent number: 11404333Abstract: A semiconductor device includes a first semiconductor die, a second semiconductor die, a dielectric layer, a first redistribution layer and a second redistribution layer. The first semiconductor die includes a first bonding pad and a second bonding pad. The second semiconductor die includes a third bonding pad and a fourth bonding pad. The dielectric layer covers the first semiconductor die and the second semiconductor die, and defines a first opening exposing the first bonding pad and the second bonding pad and a second opening exposing the third bonding pad and the fourth bonding pad. The first redistribution layer is disposed on the dielectric layer, and electrically connects the first bonding pad and the third bonding pad. The second redistribution layer is disposed on the dielectric layer, and electrically connects the second bonding pad and the fourth bonding pad.Type: GrantFiled: January 30, 2019Date of Patent: August 2, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuan-Ting Lin, Che Wei Chang, Chi-Yu Wang
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Patent number: 11374146Abstract: A semiconductor device is provided, which includes an active structure and a first semiconductor layer. The active structure includes an active region having a topmost surface and a bottommost surface, and a first dopant distributing from the topmost surface to the bottommost surface. The first semiconductor layer is located under the active structure and includes a second dopant. The active region includes a semiconductor material including As.Type: GrantFiled: May 15, 2020Date of Patent: June 28, 2022Assignee: EPISTAR CORPORATIONInventors: Meng-Yang Chen, Yuan-Ting Lin
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Publication number: 20200365757Abstract: A semiconductor device is provided, which includes an active structure and a first semiconductor layer. The active structure includes an active region having a topmost surface and a bottommost surface, and a first dopant distributing from the topmost surface to the bottommost surface. The first semiconductor layer is located under the active structure and includes a second dopant. The active region includes a semiconductor material including As.Type: ApplicationFiled: May 15, 2020Publication date: November 19, 2020Inventors: Meng-Yang CHEN, Yuan-Ting LIN
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Publication number: 20200243406Abstract: A semiconductor device includes a first semiconductor die, a second semiconductor die, a dielectric layer, a first redistribution layer and a second redistribution layer. The first semiconductor die includes a first bonding pad and a second bonding pad. The second semiconductor die includes a third bonding pad and a fourth bonding pad. The dielectric layer covers the first semiconductor die and the second semiconductor die, and defines a first opening exposing the first bonding pad and the second bonding pad and a second opening exposing the third bonding pad and the fourth bonding pad. The first redistribution layer is disposed on the dielectric layer, and electrically connects the first bonding pad and the third bonding pad. The second redistribution layer is disposed on the dielectric layer, and electrically connects the second bonding pad and the fourth bonding pad.Type: ApplicationFiled: January 30, 2019Publication date: July 30, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yuan-Ting LIN, Che Wei CHANG, Chi-Yu WANG
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Patent number: 9773753Abstract: A semiconductor device includes a first die, a second die, an encapsulant, a first dielectric layer, and at least one first trace. The first die includes a first surface and a second surface opposite to the first surface and includes at least one first pad disposed adjacent to the first surface of the first die. The second die includes a first surface and a second surface opposite to the first surface and includes at least one second pad disposed adjacent to the first surface of the second die. The first dielectric layer is disposed on at least a portion of the first surface of the first die and at least a portion of the first surface of the second die. The first trace is disposed on the first dielectric layer, which connects the first pad to the second pad, and the first trace comprises an end portion disposed adjacent to the first pad and a body portion, and the end portion extends at an angle ?1 relative to a direction of extension of the body portion.Type: GrantFiled: November 18, 2016Date of Patent: September 26, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuan-Ting Lin, Chi-Yu Wang, Wei-Hong Lai, Chin-Li Kao
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Publication number: 20080178931Abstract: A photovoltaic device having multi-junction nanostructures deposited as a multi-layered thin film on a substrate. Preferably, the device is grown as InxGa1-xN multi-layered junctions with the gradient x, where x is any value in the range from zero to one. The nanostructures are preferably 5-500 nanometers and more preferably 10-20 nanometers in diameter. The values of x are selected so that the bandgap of each layer is varied from 0.7 eV to 3.4 eV to match as nearly as possible the solar energy spectrum of 0.4 eV-4 eV.Type: ApplicationFiled: January 24, 2008Publication date: July 31, 2008Inventors: Hye-Won Seo, Li-Wei Tu, Cheng-Ying Ho, Chang-Kong Wang, Yuan-Ting Lin