Patents by Inventor Yuanbin Guo
Yuanbin Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11874896Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.Type: GrantFiled: December 11, 2020Date of Patent: January 16, 2024Assignee: Marvell Asia Pte, LtdInventors: Yuanbin Guo, Hong Jik Kim
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Patent number: 11874895Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.Type: GrantFiled: December 9, 2020Date of Patent: January 16, 2024Assignee: Marvell Asia Pte, LtdInventors: Yuanbin Guo, Hong Jik Kim
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Patent number: 11829322Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.Type: GrantFiled: December 16, 2020Date of Patent: November 28, 2023Assignee: Marvell Asia Pte, Ltd.Inventors: Yuanbin Guo, Hong Jik Kim
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Publication number: 20230261845Abstract: Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats. In an exemplary embodiment, an apparatus includes a dynamic acknowledgement (ACK) list allocation circuit that generates a dynamic ACK list that includes one or two most likely ACK candidates, and a top-Q candidate CQI bits detector that dynamically allocates a detection branch to each of the one or two most likely ACK candidates to detect top-Q candidate CQI bits. The apparatus also includes a merger circuit that mergers the top-Q candidate CQI bits detected for the one or two most likely ACK candidates to generate a merged list, a top-Q CQI symbol generator that generates top-Q CQI symbols for the top-Q candidate CQI bits detected for the one or two most likely ACK candidates, and a joint detector that detects transmitted CQI bits and ACK bits.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Applicant: Marvell Asia Pte, Ltd.Inventor: Yuanbin Guo
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Publication number: 20230247636Abstract: Methods and apparatus for channel detection in an uplink shared control channel. In an exemplary embodiment, a method includes generating soft-combined bit streams for an acknowledgement (ACK) indicator, rank indicator (RI), and channel quality indicator (CQI) received in an uplink shared channel. The method also includes decoding the ACK, RI, and CQI soft-combined bit streams to generate Top-M decoded bit streams for each indicator, and generating Top-Q symbols for each indicator from the Top-M decoded bit streams for each indicator. The method also includes calculating metrics from the Top-Q symbols and uplink control information (UCI) symbols extracted from the uplink shared channel, combining the metrics to form a search space, and searching the search space to determine transmitted ACK, RI, and CQI bits.Type: ApplicationFiled: April 10, 2023Publication date: August 3, 2023Applicant: Marvell Asia Pte, Ltd.Inventor: Yuanbin Guo
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Patent number: 11700104Abstract: Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats. In an exemplary embodiment, an apparatus includes a dynamic acknowledgement (ACK) list allocation circuit that generates a dynamic ACK list that includes one or two most likely ACK candidates, and a top-Q candidate CQI bits detector that dynamically allocates a detection branch to each of the one or two most likely ACK candidates to detect top-Q candidate CQI bits. The apparatus also includes a merger circuit that mergers the top-Q candidate CQI bits detected for the one or two most likely ACK candidates to generate a merged list, a top-Q CQI symbol generator that generates top-Q CQI symbols for the top-Q candidate CQI bits detected for the one or two most likely ACK candidates, and a joint detector that detects transmitted CQI bits and ACK bits.Type: GrantFiled: December 11, 2020Date of Patent: July 11, 2023Assignee: Marvell Asia Pte Ltd.Inventor: Yuanbin Guo
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Patent number: 11690057Abstract: Methods and apparatus for detecting ACK/NACK bits with dual list-RM decoder and symbol regeneration for PUCCH format 3. In an exemplary embodiment, a method is provided for detected ACK/NACK bits received in a long-term evolution (LTE) physical uplink control channel (PUCCH) Format 3 uplink transmission. The method includes generating Top-M ACK candidates from a descrambled bit stream, regenerating Top-M candidate symbols from the Top-M ACK candidates, calculating channel estimates for the Top-M candidate symbols, combining to the channel estimates generate a combined metric; and searching the combined metric to determine detected ACK bits.Type: GrantFiled: June 25, 2021Date of Patent: June 27, 2023Inventor: Yuanbin Guo
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Patent number: 11627564Abstract: Methods and apparatus for channel detection in an uplink shared control channel. In an exemplary embodiment, a method includes generating soft-combined bit streams for an acknowledgement (ACK) indicator, rank indicator (RI), and channel quality indicator (CQI) received in an uplink shared channel. The method also includes decoding the ACK, RI, and CQI soft-combined bit streams to generate Top-M decoded bit streams for each indicator, and generating Top-Q symbols for each indicator from the Top-M decoded bit streams for each indicator. The method also includes calculating metrics from the Top-Q symbols and uplink control information (UCI) symbols extracted from the uplink shared channel, combining the metrics to form a search space, and searching the search space to determine transmitted ACK, RI, and CQI bits.Type: GrantFiled: April 12, 2021Date of Patent: April 11, 2023Assignee: Marvell Asia Pte Ltd.Inventor: Yuanbin Guo
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Publication number: 20220116174Abstract: Methods and apparatus for symbol-to-symbol multiplexing of control, data, and reference signals on a 5G uplink. In one aspect, a job descriptor generator is configured to calculate mapping parameters for each symbol based on high level configuration parameters. A data/UCI multiplexing job engine, which is coupled to the job descriptor generator, provides symbol-based multiplexing and mapping which includes calculating reserved locations for PTRS and DMRS based on frequency-domain mapping of both PTRS and DMRS and multiplexing of data and controls from calculated intermediate parameters. A downstream processor is coupled to the job engine and configured to modulate data and control REs and insert DMRS or PTRS. In one example, the job descriptor generator is a configurable DSP processor and the job engine is an ASIC hardware accelerator.Type: ApplicationFiled: December 17, 2021Publication date: April 14, 2022Applicant: Marvell Asia Pte, Ltd.Inventors: Yuanbin Guo, Hong Jik Kim
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Patent number: 11239964Abstract: Methods and apparatus for symbol-to-symbol multiplexing of control, data, and reference signals on a 5G uplink. In one aspect, a job descriptor generator is configured to calculate mapping parameters for each symbol based on high level configuration parameters. A data/UCI multiplexing job engine, which is coupled to the job descriptor generator, provides symbol-based multiplexing and mapping which includes calculating reserved locations for PTRS and DMRS based on frequency-domain mapping of both PTRS and DMRS and multiplexing of data and controls from calculated intermediate parameters. A downstream processor is coupled to the job engine and configured to modulate data and control REs and insert DMRS or PTRS. In one example, the job descriptor generator is a configurable DSP processor and the job engine is an ASIC hardware accelerator.Type: GrantFiled: May 1, 2019Date of Patent: February 1, 2022Assignee: Marvell Asia Pte, Ltd.Inventors: Yuanbin Guo, Hong Jik Kim
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Publication number: 20210329639Abstract: Methods and apparatus for detecting ACK/NACK bits with dual list-RM decoder and symbol regeneration for PUCCH format 3. In an exemplary embodiment, a method is provided for detected ACK/NACK bits received in a long-term evolution (LTE) physical uplink control channel (PUCCH) Format 3 uplink transmission. The method includes generating Top-M ACK candidates from a descrambled bit stream, regenerating Top-M candidate symbols from the Top-M ACK candidates, calculating channel estimates for the Top-M candidate symbols, combining to the channel estimates generate a combined metric; and searching the combined metric to determine detected ACK bits.Type: ApplicationFiled: June 25, 2021Publication date: October 21, 2021Applicant: Marvell Asia Pte, Ltd.Inventor: Yuanbin Guo
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Publication number: 20210235443Abstract: Methods and apparatus for channel detection in an uplink shared control channel. In an exemplary embodiment, a method includes generating soft-combined bit streams for an acknowledgement (ACK) indicator, rank indicator (RI), and channel quality indicator (CQI) received in an uplink shared channel. The method also includes decoding the ACK, RI, and CQI soft-combined bit streams to generate Top-M decoded bit streams for each indicator, and generating Top-Q symbols for each indicator from the Top-M decoded bit streams for each indicator. The method also includes calculating metrics from the Top-Q symbols and uplink control information (UCI) symbols extracted from the uplink shared channel, combining the metrics to form a search space, and searching the search space to determine transmitted ACK, RI, and CQI bits.Type: ApplicationFiled: April 12, 2021Publication date: July 29, 2021Applicant: Marvell Asia Pte, Ltd.Inventor: Yuanbin Guo
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Patent number: 11076407Abstract: Methods and apparatus for detecting ACK/NACK bits with dual list-RM decoder and symbol regeneration for PUCCH format 3. In an exemplary embodiment, a method is provided for detected ACK/NACK bits received in a long-term evolution (LTE) physical uplink control channel (PUCCH) Format 3 uplink transmission. The method includes generating Top-M ACK candidates from a descrambled bit stream, regenerating Top-M candidate symbols from the Top-M ACK candidates, calculating channel estimates for the Top-M candidate symbols, combining to the channel estimates generate a combined metric; and searching the combined metric to determine detected ACK bits.Type: GrantFiled: January 31, 2019Date of Patent: July 27, 2021Assignee: Marvell Asia Pte, Ltd.Inventor: Yuanbin Guo
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Patent number: 10999826Abstract: Methods and apparatus for channel detection in an uplink shared control channel. In an exemplary embodiment, a method includes generating soft-combined bit streams for an acknowledgement (ACK) indicator, rank indicator (RI), and channel quality indicator (CQI) received in an uplink shared channel. The method also includes decoding the ACK, RI, and CQI soft-combined bit streams to generate Top-M decoded bit streams for each indicator, and generating Top-Q symbols for each indicator from the Top-M decoded bit streams for each indicator. The method also includes calculating metrics from the Top-Q symbols and uplink control information (UCI) symbols extracted from the uplink shared channel, combining the metrics to form a search space, and searching the search space to determine transmitted ACK, RI, and CQI bits.Type: GrantFiled: September 15, 2019Date of Patent: May 4, 2021Assignee: Cavium, LLCInventor: Yuanbin Guo
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Publication number: 20210103551Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.Type: ApplicationFiled: December 16, 2020Publication date: April 8, 2021Applicant: Cavium, LLCInventors: Yuanbin Guo, Hong Jik Kim
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Publication number: 20210099273Abstract: Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats. In an exemplary embodiment, an apparatus includes a dynamic acknowledgement (ACK) list allocation circuit that generates a dynamic ACK list that includes one or two most likely ACK candidates, and a top-Q candidate CQI bits detector that dynamically allocates a detection branch to each of the one or two most likely ACK candidates to detect top-Q candidate CQI bits. The apparatus also includes a merger circuit that mergers the top-Q candidate CQI bits detected for the one or two most likely ACK candidates to generate a merged list, a top-Q CQI symbol generator that generates top-Q CQI symbols for the top-Q candidate CQI bits detected for the one or two most likely ACK candidates, and a joint detector that detects transmitted CQI bits and ACK bits.Type: ApplicationFiled: December 11, 2020Publication date: April 1, 2021Applicant: Cavium, LLCInventor: Yuanbin Guo
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Publication number: 20210097129Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.Type: ApplicationFiled: December 11, 2020Publication date: April 1, 2021Applicant: Cavium, LLCInventors: Yuanbin Guo, Hong Jik Kim
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Publication number: 20210089609Abstract: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.Type: ApplicationFiled: December 9, 2020Publication date: March 25, 2021Applicant: Cavium, LLCInventors: Yuanbin Guo, Hong Jik Kim
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Patent number: 10891256Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.Type: GrantFiled: February 11, 2019Date of Patent: January 12, 2021Assignee: Cavium, LLCInventors: Yuanbin Guo, Hong Jik Kim
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Patent number: 10892876Abstract: Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats. In an exemplary embodiment, an apparatus includes a dynamic acknowledgement (ACK) list allocation circuit that generates a dynamic ACK list that includes one or two most likely ACK candidates, and a top-Q candidate CQI bits detector that dynamically allocates a detection branch to each of the one or two most likely ACK candidates to detect top-Q candidate CQI bits. The apparatus also includes a merger circuit that mergers the top-Q candidate CQI bits detected for the one or two most likely ACK candidates to generate a merged list, a top-Q CQI symbol generator that generates top-Q CQI symbols for the top-Q candidate CQI bits detected for the one or two most likely ACK candidates, and a joint detector that detects transmitted CQI bits and ACK bits.Type: GrantFiled: October 1, 2018Date of Patent: January 12, 2021Assignee: Cavium, LLCInventor: Yuanbin Guo