Patents by Inventor Yuan-Feng Chen
Yuan-Feng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11991882Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.Type: GrantFiled: November 16, 2021Date of Patent: May 21, 2024Assignee: MACRONIX International Co., Ltd.Inventors: Yao-An Chung, Yuan-Chieh Chiu, Ting-Feng Liao, Kuang-Wen Liu, Kuang-Chao Chen
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Patent number: 11984419Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.Type: GrantFiled: July 26, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
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Publication number: 20100155858Abstract: The present invention discloses a semiconductor device with an asymmetric channel extension structure capable of storing charges, improving gate oxide reliability, reducing parasitic capacitance and adjusting its channel extension current or turn-on resistance. A gate dielectric is formed on the semiconductor substrate. A gate is formed on the gate dielectric. A first isolation layer is formed over the sidewall of the gate. Dielectric spacers are formed on the sidewall of the first isolation layer. And at least one of the p-n junctions of source and drain regions is formed under the dielectric spacers. A fringing field induced extension region formed adjacent to asymmetric channel under gate dielectric and close to at least one of said doped regions. A threshold voltage adjustment implantation region formed under gate dielectric An anti-punch-through implantation region formed under threshold voltage adjustment implantation region.Type: ApplicationFiled: March 2, 2010Publication date: June 24, 2010Inventor: Yuan-Feng CHEN
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Patent number: 7741697Abstract: The present invention discloses a semiconductor device, the device comprising a semiconductor layer on a substrate. A gate oxide and a gate electrode are formed on the semiconductor substrate. A gate conductive layer is formed on the gate electrode. A first doped region is formed in the semiconductor layer. A dielectric spacer is optionally formed onto the sidewall of the gate electrode and part of the semiconductor layer. A second doped region is formed from a predetermined distance to the gate electrode, wherein the predetermined distance is no less than the distance between the first doped region and the gate electrode. A third doped region is formed adjacent to the first doped region in the semiconductor layer and between the first doped region and the second doped region.Type: GrantFiled: April 17, 2007Date of Patent: June 22, 2010Assignee: Applied Intellectual Properties Co., Ltd.Inventor: Yuan-Feng Chen
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Publication number: 20090057784Abstract: The present invention discloses a semiconductor device with tailored extension structure comprising a semiconductor substrate. A gate dielectric is formed on the semiconductor substrate. A gate is formed on the gate dielectric. A first isolation layer is formed over the sidewall of the gate. Dielectric spacers are formed on the sidewall of the first isolation layer. And at least one of the p-n junctions of source and drain regions is formed under the dielectric spacers and therefore forming the fringing field induced extension region. Silicide layer is formed on the gate or the doped regions. The first dielectric layer is formed over the silicide layer, dielectric spacer and portion of semiconductor substrate. The second dielectric layer is formed over the first dielectric layer. A metal plug or interconnecting structure is formed in the first dielectric layer and second dielectric layer to electrically connect to at least one of doped regions.Type: ApplicationFiled: September 4, 2007Publication date: March 5, 2009Inventor: Yuan-Feng Chen
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Publication number: 20090027942Abstract: A memory unit comprising a gate electrode, a gate dielectric under said gate electrode, an active area and a metal-semiconductor compound layer is provided. The active area comprises a first source/drain region, a second source/drain region, a normal field channel region formed under said gate electrode, a fringing field channel region formed between said first source/drain region and said normal field channel region, a pocket implantation region formed under the fringing or normal field channel regions and an extension doping region formed between said second source/drain region and said normal field channel region. The metal-semiconductor compound layer is formed over said gate electrode, first source/drain region and second source/drain region.Type: ApplicationFiled: October 6, 2008Publication date: January 29, 2009Applicant: APPLIED INTERLLECTUAL PROPERTIESInventors: YUAN-FENG CHEN, TZU-SHIH YEN, ERIK S. JENG
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Publication number: 20080258217Abstract: The present invention discloses a semiconductor device, the device comprising a semiconductor layer on a substrate. A gate oxide and a gate electrode are formed on the semiconductor substrate. A gate conductive layer is formed on the gate electrode. A first doped region is formed in the semiconductor layer. A dielectric spacer is optionally formed onto the sidewall of the gate electrode and part of the semiconductor layer. A second doped region is formed from a predetermined distance to the gate electrode, wherein the predetermined distance is no less than the distance between the first doped region and the gate electrode. A third doped region is formed adjacent to the first doped region in the semiconductor layer and between the first doped region and the second doped region.Type: ApplicationFiled: April 17, 2007Publication date: October 23, 2008Inventor: Yuan-Feng Chen