Patents by Inventor Yuanhan LI

Yuanhan LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Verification system and verification method for Ethernet interface chip
    Patent number: 11868288
    Abstract: Provided is a verification system and a verification method for an Ethernet interface chip. The verification system comprises a Reconciliation Sublayer (RS), a Physical Coding Sublayer (PCS), a Physical Medium Attachment (PMA) layer, and a flow control unit connecting the RS and the PMA layer, wherein the PMA layer is provided with a PMA clock and a buffer, the buffer is configured to store data transferred from the PCS, and the PMA clock is configured to control the PMA layer to send the data in the buffer to an Ethernet interface chip to be tested.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: January 9, 2024
    Assignee: SUZHOU CENTEC COMMUNICATIONS CO., LTD.
    Inventors: Yuanhan Li, Dong Wang, Chunjian Yuan, Mingda Zhang
  • Verification System and Verification Method for Ethernet Interface Chip
    Publication number: 20220374371
    Abstract: Provided is a verification system and a verification method for an Ethernet interface chip. The verification system comprises a Reconciliation Sublayer (RS), a Physical Coding Sublayer (PCS), a Physical Medium Attachment (PMA) layer, and a flow control unit connecting the RS and the PMA layer, wherein the PMA layer is provided with a PMA clock and a buffer, the buffer is configured to store data transferred from the PCS, and the PMA clock is configured to control the PMA layer to send the data in the buffer to an Ethernet interface chip to be tested.
    Type: Application
    Filed: October 23, 2020
    Publication date: November 24, 2022
    Inventors: Yuanhan LI, Dong WANG, Chunjian YUAN, Mingda ZHANG