Abstract: A bump array structure for an integrated circuit is presented. An array of metal alloy bumps is disposed on a surface of the integrated circuit. The array of metal alloy bumps is configured to receive input from a multi-layer substrate package and transmit output to the multi-layer substrate package. The array defines a first portion of metal alloy bumps around the periphery of the surface of the integrated circuit configured to provide power and ground signals for the integrated circuit. The array further defines a second portion of metal alloy bumps providing power and ground for the integrated circuit, located between opposing sides of the periphery of the integrated circuit. Metal alloy bumps not contained in either the first or the second portion of the array are configured for input and output signals between the integrated circuit and the multi-level substrate package.

Abstract: Provided is an IC package.

Abstract: The present invention is directed to a method and electronic computer package that is formed by placing an integrated circuit, having a plurality of bonding pads with solder bumps deposited thereon, in contact with the substrate so that one of the plurality of solder bumps is in superimposition with respect to one of the contacts and one of the plurality of bonding pads, with a volume being defined between region of the substrate in superimposition with the integrated circuit. A portion of the volume is filled with a quantity of underfill. A fluid flow bather is formed on the substrate and defines a perimeter of the volume, defining a flow restricted region. The fluid flow barrier has dimensions sufficient to control the quantity of underfill egressing from the flow restricted region.

Abstract: Broadly speaking, the present invention fills these needs by providing a lead frame package including a substrate stack having opposed sides, one of which includes a plurality of signal traces, with the remaining side including a ground plane. An integrated circuit is mounted to the substrate stack. The integrated circuit includes a plurality of bond pads. A plurality of leads is in electrical communication with a subset of the plurality of signal traces. A plurality of electrically conductive elements placing a sub-group of the plurality of bond pads in electrical communication with a sub-part of the plurality of electrically leads by being bonded signal traces of the subset, spaced-apart from the plurality of leads.

Abstract: The present invention is directed to a method and electronic computer package that is formed by placing an integrated circuit, having a plurality of bonding pads with solder bumps deposited thereon, in contact with the substrate so that one of the plurality of solder bumps is in superimposition with respect to one of the contacts and one of the plurality of bonding pads, with a volume being defined between region of the substrate in superimposition with the integrated circuit. A portion of the volume is filled with a quantity of underfill. A fluid flow barrier is formed on the substrate and defines a perimeter of the volume, defining a flow restricted region. The fluid flow barrier has dimensions sufficient to control the quantity of underfill egressing from the flow restricted region.

Abstract: A bump array structure for an integrated circuit is presented. An array of metal alloy bumps is disposed on a surface of the integrated circuit. The array of metal alloy bumps is configured to receive input from a multi-layer substrate package and transmit output to the multi-layer substrate package. The array defines a first portion of metal alloy bumps around the periphery of the surface of the integrated circuit configured to provide power and ground signals for the integrated circuit. The array further defines a second portion of metal alloy bumps providing power and ground for the integrated circuit, located between opposing sides of the periphery of the integrated circuit.

Abstract: A Ball Grid Array (BGA) integrated circuit package having (i) an additional dedicated ground ring on the package substrate which provides a reduced area return current loop path to reduce wire bond inductance; and/or (ii) ground wires positioned between adjacent input/output wires on the substrate which provide additional transient current paths among the input/output wires for improved characteristic impedance and cross talk control.

Abstract: A method of distributing an array of interconnects on an electronic device divides the array into multiple regions, each region having certain performance requirements. For each region, predefined performance curves are used to choose from a plurality of interconnect distribution pattern modules one or more interconnect distribution pattern modules that satisfy the corresponding performance requirements. The chosen interconnect distribution pattern modules are used to generate a performance indication map highlighting those vulnerable interconnect(s) that may suffer severe crosstalk interference. Each vulnerable interconnect is then relocated to a different location until the performance requirements are met.

Abstract: A package substrate is provided with a side/edge-mounted decoupling capacitor that can provide substantially instant power or control simultaneous switching noise (SSN) associated with a semiconductor device package. A fabrication method for such a package substrate is also provided. Further, a semiconductor device package that includes such a package substrate is provided. According to various embodiments, the decoupling capacitor is connected to edges or sides of a power plane and a ground plane in the package substrate for connection via the semiconductor device package's power delivery system to a power source or component.

Abstract: Methods and apparatus are provided for designing the electrical interconnects of a substrate. Modules are used to design sections of the electrical interconnects. Multiple modules may be interconnected to generate the electrical interconnects. The placement of modules and/or the interconnection of the modules may depend on a netlist and/or a separate report. Modules may even be defined by various constraints. Accordingly, a module based design may be implemented for efficiently and effectively producing a standardized electrical interconnect design.

Abstract: A flip chip packaging technique and associated apparatus that consolidates many or all of the steps in a conventional flip chip packaging process results in substantially decreased packaging time, e.g., only one to two hours, complexity, e.g., requiring fewer pieces and much simpler equipment, and cost, arising from reduced equipment operation and maintenance time and decreased labor. An assembly fixture useful for implementing the consolidated assembly technique engages and holds in place a semiconductor flip chip die with a plurality semiconductor package components in a desired package configuration so that they can be assembled into a semiconductor package with a single application of heat and pressure.

Abstract: A flip chip packaging technique and associated apparatus that consolidates many or all of the steps in a conventional flip chip packaging process results in substantially decreased packaging time, e.g., only one to two hours, complexity, e.g., requiring fewer pieces and much simpler equipment, and cost, arising from reduced equipment operation and maintenance time and decreased labor. An assembly fixture useful for implementing the consolidated assembly technique engages and holds in place a semiconductor flip chip die with a plurality semiconductor package components in a desired package configuration so that they can be assembled into a semiconductor package with a single application of heat and pressure.