Abstract: A method and apparatus for auto-generation of shift register file for high-level synthesis compiler includes parsing input source codes for specific definition of shift register file, a plurality of compiler directives to indicate the shift register file name, shift register file size, shift register file read access order, and shift register file write timing of the specific shift register file. The invention also includes determining the shifting interval of shift register file with specific definition after each reading or writing automatically. The invention further includes determining if the shift register file with specific definition has been generated, generating shift register file with specific definition if it has not been generated, and generating shift register file control signals to access the shift register file with specific definition.

Abstract: A method and apparatus to produce high-level synthesis Register Transfer Level designs utilises power management formulations can be used to gear the allocation process to generate hardware architecture of minimal spurious switching. Bipartite weighted Assignment is used to determine the sharing of functional units, through cost formulations and the Hungarian Algorithm.

Abstract: An apparatus and a method for efficient decoding progressive JPEG bitstreams are invented. This invention provides a memory-efficient progressive JPEG decoding method with minimal memory requirements. Instead of storing all the DCT coefficients of at particular decoding scan, a portion of DCT coefficients and the non-zero coefficient indicators for the rest of the DCT coefficients are stored in either original data format or in a compressed format. The memory requirement for decoding progressive JPEG pictures can be minimized according to the resolution of display devices in the real applications.