Patents by Inventor Yueh-Ching CHANG

Yueh-Ching CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11991859
    Abstract: An apparatus may include a heat pipe with a first portion residing in a first plane, a second portion residing in the first plane and a third portion positioned between the first portion and the second portion, the third portion residing in a second plane spaced-apart from the first plane. The apparatus further includes a base plate including an opening and a clip plate having a first region, a second region and a third region positioned between the first and the second regions. The third portion of the heat pipe is positioned within the opening, and the clip plate is coupled to the base plate such that i) the third region of the clip plate is in superimposition with the third portion of the heat pipe and ii) third region of the clip plate resides in the first plane.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: May 21, 2024
    Assignee: Dell Products L.P.
    Inventors: Chin-Chung Wu, Chun-Han Lin, Che-Jung Chang, Yueh Ching Lu
  • Patent number: 11990550
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Patent number: 11973124
    Abstract: In method of manufacturing a semiconductor device, a source/drain epitaxial layer is formed, one or more dielectric layers are formed over the source/drain epitaxial layer, an opening is formed in the one or more dielectric layers to expose the source/drain epitaxial layer, a first silicide layer is formed on the exposed source/drain epitaxial layer, a second silicide layer different from the first silicide layer is formed on the first silicide layer, and a source/drain contact is formed over the second silicide layer.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Wei Chang, Shahaji B. More, Yi-Ying Liu, Yueh-Ching Pai
  • Publication number: 20240105787
    Abstract: Embodiments of the present disclosure provide a method of forming a contact opening using selective ALE operations to remove ILD layer along an upper profile of a source/drain region, and then form a source/drain contact feature having a concave bottom profile with increased contact area.
    Type: Application
    Filed: February 1, 2023
    Publication date: March 28, 2024
    Inventors: Cheng-Wei CHANG, Shahaji B. MORE, Chi-Yu CHOU, Yueh-Ching PAI
  • Patent number: 9711468
    Abstract: A bonding pad structure comprises a first dielectric layer, a first conductive island in a second dielectric layer over the first dielectric layer and a via array having a plurality of vias in a third dielectric layer over the first conductive island. The structure also comprises a plurality of second conductive islands in a fourth dielectric layer over the via array. The second conductive islands are each separated from one another by a dielectric material of the fourth dielectric layer and in contact with at least one via of the via array. The structure further comprises a substrate over the second conductive islands. The substrate has an opening defined therein that exposes at least one second conductive island. The structure additionally comprises a bonding pad over the substrate. The bonding pad is in contact with the at least one second conductive island through the opening in the substrate.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Han Tsai, Jung-Chi Jeng, Yueh-Ching Chang, Volume Chien, Huang-Ta Huang, Chi-Cherng Jeng
  • Publication number: 20150214165
    Abstract: A bonding pad structure comprises a first dielectric layer, a first conductive island in a second dielectric layer over the first dielectric layer and a via array having a plurality of vias in a third dielectric layer over the first conductive island. The structure also comprises a plurality of second conductive islands in a fourth dielectric layer over the via array. The second conductive islands are each separated from one another by a dielectric material of the fourth dielectric layer and in contact with at least one via of the via array. The structure further comprises a substrate over the second conductive islands. The substrate has an opening defined therein that exposes at least one second conductive island. The structure additionally comprises a bonding pad over the substrate. The bonding pad is in contact with the at least one second conductive island through the opening in the substrate.
    Type: Application
    Filed: April 10, 2015
    Publication date: July 30, 2015
    Inventors: Tsung-Han TSAI, Jung-Chi JENG, Yueh-Ching CHANG, Volume CHIEN, Huang-Ta HUANG, Chi-Cherng JENG
  • Patent number: 9041204
    Abstract: A bonding pad structure includes a substrate and a first conductive island formed in a first dielectric layer and disposed over the substrate. A first via array having a plurality of vias is formed in a second dielectric layer and disposed over the first conductive island. A second conductive island is formed in a third dielectric layer and disposed over the first via array. A bonding pad is disposed over the second conductive island. The first conductive island, the first via array, and the second conductive island are electrically connected to the bonding pad. The first via array is connected to no other conductive island in the first dielectric layer except the first conductive island. No other conductive island in the third dielectric layer is connected to the first via array except the second conductive island.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 26, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Han Tsai, Jung-Chi Jeng, Yueh-Ching Chang, Volume Chien, Huang-Ta Huang, Chi-Cherng Jeng
  • Publication number: 20130256893
    Abstract: A bonding pad structure includes a substrate and a first conductive island formed in a first dielectric layer and disposed over the substrate. A first via array having a plurality of vias is formed in a second dielectric layer and disposed over the first conductive island. A second conductive island is formed in a third dielectric layer and disposed over the first via array. A bonding pad is disposed over the second conductive island. The first conductive island, the first via array, and the second conductive island are electrically connected to the bonding pad. The first via array is connected to no other conductive island in the first dielectric layer except the first conductive island. No other conductive island in the third dielectric layer is connected to the first via array except the second conductive island.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Han TSAI, Jung-Chi JENG, Yueh-Ching CHANG, Volume CHIEN, Huang-Ta HUANG, Chi-Cherng JENG