Abstract: A memory device is disclosed. The memory device comprises N flash memories and a flash manager. The flash manager comprises an interleave/de-interleave buffer and an addressing circuit. The interleave/de-interleave buffer operates according to a mode signal. The addressing circuit sequentially converts N input address signals to transmit N converted address signals. For write operations, the interleave/de-interleave buffer interleaves a write parameter stream into N interleaved streams according to the mode signal indicative of interleave mode and the N interleaved streams in conjunction with the N converted address signals are written into the N flash memories in parallel. For read operations, N read streams are read from the N flash memories in parallel in response to the N converted address signals and the interleave/de-interleave buffer de-interleaves the N read streams into a de-interleaved parameter stream according to the mode signal indicative of de-interleave mode.

Abstract: The present invention provides a controlling apparatus and method for an image scanning system that includes a direct current (DC) motor and an image sensor driven by the DC motor to move. A position signal representative of the position associated of the image sensor is generated and the controlling apparatus and method is performed according to the position signal.

Abstract: The present invention provides a controlling apparatus and method for an image scanning system that includes a direct current (DC) motor and an image sensor driven by the DC motor to move. A position signal representative of the position associated of the image sensor is generated and the controlling apparatus and method is performed according to the position signal.