Abstract: Systems and methods for delaying a signal are described herein. In one embodiment, a method for delaying a signal comprises receiving a first signal edge, and, in response to receiving the first signal edge, counting a number of oscillations of an oscillator. The method also comprises outputting a second signal edge if the number of oscillations reaches a predetermined number. The second signal edge represents a delayed version of the first signal edge.

Abstract: Systems and methods for delay control are described herein. In one embodiment, a delay system comprises a first delay circuit configured to provide a voltage bias to a second delay circuit, wherein the voltage bias controls a delay of the second delay circuit, and to update the voltage bias at an update rate. The delay system also comprises an update controller configured to adjust the update rate of the first delay circuit. For example, the update controller may adjust the update rate based on timing requirements of a memory interface incorporating the delay system. The update rate may be reduced when the timing requirements are more relaxed to reduce power, and may be increased when the timing requirements are tighter.

Abstract: Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.

Abstract: Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.

Abstract: Systems and methods for delay control are described herein. In one embodiment, a delay system comprises a first delay circuit configured to provide a voltage bias to a second delay circuit, wherein the voltage bias controls a delay of the second delay circuit, and to update the voltage bias at an update rate. The delay system also comprises an update controller configured to adjust the update rate of the first delay circuit. For example, the update controller may adjust the update rate based on timing requirements of a memory interface incorporating the delay system. The update rate may be reduced when the timing requirements are more relaxed to reduce power, and may be increased when the timing requirements are tighter.

Abstract: Systems and methods for delaying a signal are described herein. In one embodiment, a method for delaying a signal comprises receiving a first signal edge, and, in response to receiving the first signal edge, counting a number of oscillations of an oscillator. The method also comprises outputting a second signal edge if the number of oscillations reaches a predetermined number. The second signal edge represents a delayed version of the first signal edge.

Abstract: Sense amplifiers that can provide improved resolving times can be used, for example, in clock and data recovery circuits. The sense amplifiers sense the value of a differential input signal using a latch circuit and then, after an initial sensing time, force the latch circuit to resolve a digital value that corresponds to the value of the input signal. An implementation of the sense amplifies uses a first latch with cross-coupled inverters that produce set and reset signals. A transistor pair couples the differential input signal to the cross-coupled inverters via a switch to ground. A discharge path circuit arranged to accelerate the resolving of the latch circuit is also coupled to the cross-coupled inverters. The discharge path can be enabled after an initial sensing time.

Abstract: A charge pump is disclosed herein that includes an output node configured to be coupled to a charge storage device configured to store a charge to produce a control voltage based on the charge stored in the charge storage device; a charging circuit configured to provide charge to the charge storage device; a discharging circuit configured to remove charge from the charge storage device; and an amplifier. The amplifier includes an inverting input configured to receive the control voltage from the output node as a first input signal; and, a non-inverting input configured to receive a second input signal including a bias voltage, wherein the amplifier is configured to attempt to match respective levels of the bias voltage and the control voltage when the charge in the charge storage device is changing.