Patents by Inventor Yuen Hung Chan
Yuen Hung Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10367507Abstract: A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.Type: GrantFiled: July 7, 2018Date of Patent: July 30, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Alan Bunce, Yuen Hung Chan, John D. Davis, Antonio Raffaele Pelella
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Patent number: 10320388Abstract: A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.Type: GrantFiled: July 8, 2018Date of Patent: June 11, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
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Patent number: 10312915Abstract: A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.Type: GrantFiled: July 8, 2018Date of Patent: June 4, 2019Assignee: International Business Machines CorporationInventors: Paul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
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Patent number: 10312916Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.Type: GrantFiled: July 8, 2018Date of Patent: June 4, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
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Patent number: 10224933Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.Type: GrantFiled: October 29, 2017Date of Patent: March 5, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
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Publication number: 20180367145Abstract: A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.Type: ApplicationFiled: July 7, 2018Publication date: December 20, 2018Applicant: International Business Machines CorporationInventors: Paul Alan Bunce, Yuen Hung Chan, John D. Davis, Antonio Raffaele Pelella
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Publication number: 20180323786Abstract: A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.Type: ApplicationFiled: July 8, 2018Publication date: November 8, 2018Applicant: International Business Machines CorporationInventors: Paul Alan Bunce, Yuen Hung Chan, John D. Davis, Antonio Raffaele Pelella
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Publication number: 20180323787Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.Type: ApplicationFiled: July 8, 2018Publication date: November 8, 2018Applicant: International Business Machines CorporationInventors: Paul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
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Publication number: 20180316354Abstract: A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.Type: ApplicationFiled: July 8, 2018Publication date: November 1, 2018Applicant: International Business Machines CorporationInventors: Paul Alan Bunce, Yuen Hung Chan, John D. Davis, Antonio Raffaele Pelella
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Patent number: 9966958Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.Type: GrantFiled: June 3, 2017Date of Patent: May 8, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
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Publication number: 20180091153Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.Type: ApplicationFiled: October 29, 2017Publication date: March 29, 2018Applicant: International Business Machines CorporationInventors: Paul Alan Bunce, Yuen Hung Chan, John D. Davis, Antonio Raffaele Pelella
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Publication number: 20180091152Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.Type: ApplicationFiled: June 3, 2017Publication date: March 29, 2018Applicant: International Business Machines CorporationInventors: Paul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
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Patent number: 9742408Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.Type: GrantFiled: September 23, 2016Date of Patent: August 22, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
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Patent number: 9537474Abstract: Electronic circuits and memory circuits are provided for implementing a method for transforming a chip clock signal to a local clock signal. The method includes: generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, where the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; and generating the local clock signal based on the second clock signal.Type: GrantFiled: October 26, 2015Date of Patent: January 3, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuen Hung Chan, Juergen Pille, Rolf Sautter, Tobias Werner
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Publication number: 20160344377Abstract: Electronic circuits and memory circuits are provided for implementing a method for transforming a chip clock signal to a local clock signal. The method includes: generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, where the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; and generating the local clock signal based on the second clock signal.Type: ApplicationFiled: October 26, 2015Publication date: November 24, 2016Inventors: Yuen Hung CHAN, Juergen PILLE, Rolf SAUTTER, Tobias WERNER
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Patent number: 9401698Abstract: Electronic circuits and memory circuits are provided for implementing a method for transforming a chip clock signal to a local clock signal. The method includes: generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, where the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; and generating the local clock signal based on the second clock signal.Type: GrantFiled: May 20, 2015Date of Patent: July 26, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuen Hung Chan, Juergen Pille, Rolf Sautter, Tobias Werner
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Patent number: 8837235Abstract: A local evaluation circuit for a memory array includes first and second NAND gates and first, second, third, and fourth switches. The first switch is configured to couple a first node of the second NAND gate to a first power supply node in response to a first read signal. The second switch is configured to couple a first node of the first NAND gate to the first power supply node in response to a second read signal. The third switch is configured to couple a second node of the first NAND gate to a second power supply node in response to the first read signal. The fourth switch is configured to couple a second node of the second NAND gate to the second power supply node in response to the second read signal.Type: GrantFiled: March 6, 2013Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Yuen Hung Chan, Michael Kugel, Silke Penth, Tobias Werner
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Patent number: 8325549Abstract: A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through local write bit lines, the global write bit lines configured to write a selected SRAM cell with data presented on a pair of write data input lines; a pair of complementary global read bit lines in selective communication with the array through local read bit lines, the global read bit lines configured to read data stored in a selected cell and present the read data on a pair of read data output lines; and write control logic configured to control precharging of the global write bit lines independently with respect to the global read bit lines, and wherein a pulse width of write data on the global write bit lines is determined only by a global column select signal.Type: GrantFiled: February 26, 2010Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Yuen Hung Chan, Antonia R. Pelella
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Patent number: 8325543Abstract: A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and blocking logic configured to prevent, during a write operation, propagation of stored data from the SRAM cells out on the complementary read data output lines prior to completion of the write operation.Type: GrantFiled: February 26, 2010Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Yuen Hung Chan, Antonia R. Pelella
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Publication number: 20110211400Abstract: A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and blocking logic configured to prevent, during a write operation, propagation of stored data from the SRAM cells out on the complementary read data output lines prior to completion of the write operation.Type: ApplicationFiled: February 26, 2010Publication date: September 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuen Hung Chan, Antonia R. Pelella