Patents by Inventor Yuh-Ta FAN
Yuh-Ta FAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11742393Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.Type: GrantFiled: March 1, 2022Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-nan Lin, Ding-I Liu, Yuh-Ta Fan
-
Publication number: 20230005796Abstract: The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.Type: ApplicationFiled: July 26, 2022Publication date: January 5, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Yuh-Ta FAN, Tien-Wei YU
-
Patent number: 11430700Abstract: The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.Type: GrantFiled: June 26, 2020Date of Patent: August 30, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Yuh-Ta Fan, Tien-Wei Yu
-
Patent number: 11411108Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.Type: GrantFiled: October 23, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen Chen, Chui-Ya Peng, Ching Yu, Pin-Hen Lin, Yen Chuang, Yuh-Ta Fan
-
Publication number: 20220190122Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.Type: ApplicationFiled: March 1, 2022Publication date: June 16, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-nan LIN, Ding-I Liu, Yuh-Ta Fan
-
Patent number: 11264467Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.Type: GrantFiled: August 5, 2020Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-nan Lin, Ding-I Liu, Yuh-Ta Fan
-
Publication number: 20210407861Abstract: The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Yuh-Ta FAN, Tien-Wei YU
-
Publication number: 20210351041Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.Type: ApplicationFiled: July 19, 2021Publication date: November 11, 2021Inventors: Hui-An HAN, Ding-I LIU, Yuh-Ta FAN, Kai-Shiung HSU
-
Patent number: 11069534Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.Type: GrantFiled: October 15, 2019Date of Patent: July 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hui-An Han, Ding-I Liu, Yuh-Ta Fan, Kai-Shiung Hsu
-
Publication number: 20210043771Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen CHEN, Chui-Ya PENG, Ching YU, Pin-Hen LIN, Yen CHUANG, Yuh-Ta FAN
-
Publication number: 20200365695Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.Type: ApplicationFiled: August 5, 2020Publication date: November 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-nan Lin, Ding-I Liu, Yuh-Ta Fan
-
Patent number: 10818790Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends substantially along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.Type: GrantFiled: June 7, 2019Date of Patent: October 27, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen Chen, Chui-Ya Peng, Ching Yu, Pin-Hen Lin, Yen Chuang, Yuh-Ta Fan
-
Patent number: 10749004Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.Type: GrantFiled: June 15, 2018Date of Patent: August 18, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-nan Lin, Ding-I Liu, Yuh-Ta Fan
-
Publication number: 20200135868Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.Type: ApplicationFiled: October 15, 2019Publication date: April 30, 2020Inventors: Hui-An HAN, Ding-I LIU, Yuh-Ta FAN, Kai-Shiung HSU
-
Publication number: 20190312144Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends substantially along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.Type: ApplicationFiled: June 7, 2019Publication date: October 10, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen CHEN, Chui-Ya PENG, Ching YU, Pin-Hen LIN, Yen CHUANG, Yuh-Ta FAN
-
Patent number: 10319857Abstract: A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.Type: GrantFiled: October 30, 2017Date of Patent: June 11, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen Chen, Chui-Ya Peng, Ching Yu, Pin-Hen Lin, Yen Chuang, Yuh-Ta Fan
-
Publication number: 20190006474Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.Type: ApplicationFiled: June 15, 2018Publication date: January 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-nan Lin, Ding-I Liu, Yuh-Ta Fan
-
Patent number: 10153156Abstract: According to one example, a process includes performing a first plurality of layer deposition cycles of a deposition process on a substrate, and after performing the first plurality of layer deposition cycles, performing a plasma enhanced layer deposition cycle comprising a plasma treatment process. The first plurality of layer deposition cycles are performed without a plasma treatment process.Type: GrantFiled: February 15, 2017Date of Patent: December 11, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun Hsiung Tsai, Kuo-Feng Yu, Yuh-Ta Fan
-
Publication number: 20180174820Abstract: According to one example, a process includes performing a first plurality of layer deposition cycles of a deposition process on a substrate, and after performing the first plurality of layer deposition cycles, performing a plasma enhanced layer deposition cycle comprising a plasma treatment process. The first plurality of layer deposition cycles are performed without a plasma treatment process.Type: ApplicationFiled: February 15, 2017Publication date: June 21, 2018Inventors: Chun Hsiung Tsai, Kuo-Feng Yu, Yuh-Ta Fan
-
Publication number: 20180069120Abstract: A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.Type: ApplicationFiled: October 30, 2017Publication date: March 8, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen CHEN, Chui-Ya PENG, Ching YU, Pin-Hen LIN, Yen CHUANG, Yuh-Ta FAN