Patents by Inventor Yuhan Zhu

Yuhan Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240141462
    Abstract: A method for smelting low-phosphorus high-manganese steel based on reduction dephosphorization of ferromanganese is provided in the present application, relating to the technical field of high-manganese steel smelting, where the dephosphorization of ferromanganese is carried out under reducing atmosphere conditions through mediate-frequency induction furnace to obtain molten ferromanganese with lower phosphorus content, which is subsequently mixed with low phosphorus molten steel obtained by smelting in oxidative period of electric arc furnace in LF ladle refining furnace to make the Mn content of steel reach the requirement of high-manganese steel, and smelting is carried out under the condition of reducing atmosphere by adjusting the composition and temperature of the molten steel to meet the requirements of the target composition of the steel grade before tapping the steel.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 2, 2024
    Inventors: Tao LI, Wei LIU, Chen CHEN, Fucheng ZHANG, Min TAN, Shaopeng GU, Lin ZHANG, Qian MENG, Degang WEI, Yuhan SUN, Guangbei ZHU, Aihua ZHAO
  • Patent number: 11854862
    Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: December 26, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Guangsu Shao, Deyuan Xiao, Yunsong Qiu, Youming Liu, Yi Jiang, Xingsong Su, Yuhan Zhu
  • Publication number: 20230335430
    Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 19, 2023
    Inventors: Guangsu Shao, Deyuan Xiao, Yunsong Qiu, Youming Liu, Yi Jiang, Xingsong Su, Yuhan Zhu
  • Publication number: 20230013070
    Abstract: A semiconductor device and a formation method thereof are provided. The semiconductor device includes: a semiconductor substrate, where a plurality of columnar active areas are formed on the semiconductor substrate, the plurality of columnar active areas are spaced apart by a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction; a plurality of third trenches positioned in the semiconductor substrate at bottoms of the second trenches, where the third trenches are recessed to bottoms of the columnar active areas, and a bottom surface of a given one of the third trenches is higher than a bottom surface of the given first trench; and a plurality of metal silicide bit lines extending along the first direction in the semiconductor substrate positioned at the bottoms of the plurality of third trenches and the bottoms of the plurality of columnar active areas.
    Type: Application
    Filed: September 22, 2022
    Publication date: January 19, 2023
    Inventors: Guangsu SHAO, Deyuan XIAO, Yunsong QIU, Yuhan ZHU
  • Publication number: 20220173111
    Abstract: Embodiments of the present application provide a semiconductor structure and a semiconductor structure manufacturing method. The semiconductor structure includes: a wordline; and a first bitline and a second bitline located on two sides of the wordline and a first memory structure and a second memory structure located on the two sides of the wordline. The first bitline and the second bitline are connected to the first memory structure and the second memory structure respectively through a transistor. An extension direction of the first bitline is perpendicular to an extension direction of the wordline.
    Type: Application
    Filed: February 15, 2022
    Publication date: June 2, 2022
    Inventors: Yuhan ZHU, Chuxian Liao, Zhan Ying
  • Publication number: 20220139924
    Abstract: A method for forming a semiconductor structure and the semiconductor structure are provided. The method for forming the semiconductor structure includes: providing a substrate, wherein a separate bit line structure is formed on the substrate; forming a first sacrificial layer on the side wall of the bit line structure; forming a first dielectric layer filling gap between the bit line structures; patterning the first dielectric layer and the first sacrificial layer to form a through hole, wherein the through hole and the remaining first dielectric layer and first sacrificial layer are alternately arranged; forming a second sacrificial layer on the side wall of the through hole, and filling the through hole to form a contact plug; forming a contact structure on the contact plug; and removing the first sacrificial layer to form a first air gap, and removing the second sacrificial layer to form a second air gap.
    Type: Application
    Filed: January 13, 2022
    Publication date: May 5, 2022
    Inventors: Chuxian LIAO, Yuhan ZHU, Zhan YING
  • Publication number: 20220139763
    Abstract: A forming method for a semiconductor structure and the semiconductor structure are provided. The forming method of the semiconductor structure includes: providing a substrate, wherein separate bit line structures are formed on the substrate; forming a first sacrificial layer on a sidewall of a bit line structure; forming first dielectric layer filling gaps between adjacent bit line structures; patterning a first dielectric layer to form vias, wherein the vias expose active regions of the substrate, and the vias and remaining parts of the first dielectric layers are alternately arranged in an extension direction of the bit line structures; forming a second sacrificial layer on sidewalls of a via, and filling the via to form a contact plugs; forming a contact structure on the contact plug; and removing the first sacrificial layer to form first air gap, and removing the second sacrificial layer to form a second air gap.
    Type: Application
    Filed: January 12, 2022
    Publication date: May 5, 2022
    Inventors: Chuxian Liao, Yuhan Zhu, Zhan Ying
  • Publication number: 20220102381
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a semiconductor body, bit lines and word lines. The semiconductor body includes a substrate and an isolation structure positioned above the substrate and configured to isolate a plurality of active regions, part of each of the active regions being formed from the substrate. The bit lines are positioned in the substrate and are connected to the active regions. The word lines intersect with the active regions and surround the active regions. The substrate is Silicon On Insulator (SOI) substrate.
    Type: Application
    Filed: October 18, 2021
    Publication date: March 31, 2022
    Inventors: Kui ZHANG, Yuhan ZHU, Jie LIU, Zhan YING
  • Publication number: 20220085027
    Abstract: A semiconductor structure and a semiconductor structure manufacturing method is provided. The semiconductor structure includes: a wordline; and a first bitline and a second bitline located on two sides of the wordline and a first storage structure and a second storage structure located on the two sides of the wordline, the first bitline and the second bitline being connected to the first storage structure and the second storage structure respectively through a transistor. An extension direction of the first bitline and an extension direction of the wordline are at an acute or obtuse angle. In this way, the first storage structure and the second storage structure are provided on both sides of the wordline, which can increase storage capacity.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Inventors: Yuhan ZHU, Chuxian LIAO, Zhan YING
  • Patent number: 9462076
    Abstract: The present invention provides an information dissemination system based on the integration of the broadcast network and the Internet, including: a terminal storage module, a regional storage module, a statistics-and-analysis module, a recommendation-and-analysis module, a media content management module and a network scheduling module. By two-level storing and playing of media contents, along with the statistics and analysis for on-demand behaviors of users, the intervention of the operator, and the recommendation and analysis performed by the recommendation-and-analysis module, the media contents are classified. Further, according to the classification, a media content is transmitted to the terminal storage module via the Internet; or, is transmitted to the terminal storage module via the Internet and pushed to the terminal storage module via the broadcast network; or, is pushed to the terminal storage module or the regional storage module at a predetermined time via the broadcast network.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: October 4, 2016
    Assignee: CHINA RADIO INTERNATIONAL
    Inventors: Lian Wang, Xiaoyan Ren, Zizhong Zhao, Yulin Chen, Wei Xin, Min Wu, Yuhan Zhu, Xin Wang
  • Publication number: 20150134731
    Abstract: The present invention provides an information dissemination system based on the integration of the broadcast network and the Internet, including: a terminal storage module, a regional storage module, a statistics-and-analysis module, a recommendation-and-analysis module, a media content management module and a network scheduling module. By two-level storing and playing of media contents, along with the statistics and analysis for on-demand behaviors of users, the intervention of the operator, and the recommendation and analysis performed by the recommendation-and-analysis module, the media contents are classified. Further, according to the classification, a media content is transmitted to the terminal storage module via the Internet; or, is transmitted to the terminal storage module via the Internet and pushed to the terminal storage module via the broadcast network; or, is pushed to the terminal storage module or the regional storage module at a predetermined time via the broadcast network.
    Type: Application
    Filed: May 24, 2013
    Publication date: May 14, 2015
    Inventors: Lian Wang, Xiaoyan Ren, Zizhong Zhao, Yulin Chen, Wei Xin, Min Wu, Yuhan Zhu, Xin Wang
  • Patent number: D986889
    Type: Grant
    Filed: February 12, 2023
    Date of Patent: May 23, 2023
    Inventor: Yuhan Zhu
  • Patent number: D988323
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: June 6, 2023
    Inventor: Yuhan Zhu
  • Patent number: D1021905
    Type: Grant
    Filed: October 11, 2023
    Date of Patent: April 9, 2024
    Assignee: ADM TECH LLC
    Inventor: Yuhan Zhu