Abstract: A registration device (10) includes an extracting unit (131) that extracts inner header information and outer header information of an encapsulated packet, a filter unit (132) that calculates a hash value of the inner header information and the outer header information as an address of a hash table in which arrival information indicating whether a first packet of a series of flow has arrived is registered for each address and causes, based on the hash table, inner header information and outer header information of the first packet of the series of flow to pass, and a registering unit (133) that registers the inner header information and the outer header information of the first packet, which the filter unit (132) has caused to pass, in a database in association with each other.

Abstract: A continuity checking apparatus generates a continuity checking packet to which a predetermined flag and user attributes are assigned and transmits the generated continuity checking packet to an edge router connected to a service that is an entrance of a service chain. Each service transmits an arrival message with respect to the continuity checking packet to the continuity checking apparatus upon reception of the continuity checking packet to which the predetermined flag is assigned. In addition, each service transfers the continuity checking packet to a next service device of the service chain on the basis of the user attributes assigned to the received continuity checking packet. The continuity checking apparatus identifies a path representing service devices through which the continuity checking packet passes on the basis of the arrival message transmitted from each service, and determines whether the identified path is the same as a path of the service chain that is a continuity checking target.

Abstract: The embodiments disclosed herein describe a switching ASIC that provides a dynamic single-bit routing and multiplexing function in an emulation system. The switching ASIC may receive a set of incoming data streams from a first set of emulation devices (e.g., emulation ASICs), disassemble each data stream to the constituent bits, dynamically multiplex the bits, reassemble the multiplexed bits into outgoing data streams, and transmit the outgoing data streams to a second set of emulation devices. Multiple statically scheduled selection tables (UCSWs), one for each output lane of the switching ASIC, drive the selection and routing of bits from input slots of various input lanes to the output slots of the output lane.

Abstract: Using a framing protocol, an application specific integrated circuit (ASIC) in an emulation system may transmit a start-of-packet molecule to a serializer-deserializer (SerDes) interface of a switching ASIC in a gap cycle leading up to an emulation cycle such that the switching ASIC may start routing mission data through the SerDes interface during the emulation cycle. The ASIC may transmit an end-of-packet molecule at a first gap cycle to the SerDes interface of the switching ASIC such that the switching ASIC may stop routing data through the SerDes interface during the gap cycles. The start-of-packet molecule may include a start-of-packet word, a status word, cyclic redundancy check word, and an idle word. The end-of-packet molecule may include an end-of-packet word, a status word, a cyclic redundancy check word, and an idle word.

Abstract: A feature calculation unit (15b) calculates a feature of header information of a packet. A classification unit (15c) classifies the packet as a normal packet or an abnormal packet by using the calculated feature. An adding unit (15d) adds a label indicating a tool name of a known attack tool to header information of a packet attacked using the attack tool. A learning unit (15e) learns the addition of the label by using the label and the feature calculated for the packet to which the label has been added as teacher data.

Abstract: An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.

Abstract: The controller (10) acquires information about the band of the flow within the tunnel and the band of each flow after policing or shaping, calculates the ratio of the traffic volume after policing or shaping to the traffic volume before policing or shaping by using the acquired information about the band, and estimates the traffic volume of the flow to be monitored within the tunnel by using the calculated ratio and the band of each flow after policing or shaping.

Abstract: A copy unit (11c) copies packets received from a network. A compression unit (11d) compresses the payload of each of the copied packets and transfers each of the compressed packets to a security apparatus (20a). A storage unit stores filter information identifying the attack packet detected by the security apparatus, and a discarding unit (11a) uses the filter information to discard the attack packet. The storage unit stores an assignment rule designating a processing method for each predetermined flow of the network traffic, and an assignment unit (11b) uses the assignment rule to assign each of the packets received from the network to a copy unit (11c) or to another security apparatus (20b), for each of the predetermined flows.

Abstract: A compaction circuit in an emulation system may store in a data array emulation data that may be read in subsequent emulation steps. For each emulation step, the compaction circuit may receive keeptags from a local control store word of the emulation step and store portions of emulation data identified by the keeptags. The keeptags in the control store words may be inserted by a compiler based upon whether a corresponding read port of emulation processor reads the stored data in the subsequent steps. The compaction circuit may also translate the logical read address of the stored data to a physical read address in the shared data array. A dynamic modification engine may enable dynamic modification of netlists while using the compacted data array. In response to a request, the dynamic modification engine may modify one or more keeptags and update read addresses in the control store words.

Abstract: A collection device (10) collects traffic from a core network (10N) connected to a plurality of operator networks (20N). Further, an analysis device has a plurality of functions of analyzing traffic. Further, a setting device sets a scenario that designates at least one of the plurality of functions. Further, a pre-processing device converts the traffic collected by the collection device (10) to traffic of a format suitable for the function designated by the scenario. Further, a distribution device distributes the traffic converted by the pre-processing device to a designated function.

Abstract: A compaction circuit in an emulation system may store in a data array emulation data that may be read in subsequent emulation steps. For each emulation step, the compaction circuit may receive keeptags from a local control store word of the emulation step and store portions of emulation data identified by the keeptags. The keeptags in the control store words may be inserted by a compiler based upon whether a corresponding read port of emulation processor reads the stored data in the subsequent steps. The compaction circuit may also translate the logical read address of the stored data to a physical read address in the shared data array. A dynamic modification engine may enable dynamic modification of netlists while using the compacted data array. In response to a request, the dynamic modification engine may modify one or more keeptags and update read addresses in the control store words.

Abstract: An emulation system may have a built-in self-test circuit to generate one or more built-in self-test instructions. The one or more built-in self-test instructions may be pseudorandom. The one or more built-in self-test instructions may cause one or more emulation processors of the emulation system to generate one or more deterministic outputs. A testing processor of the emulation system may compare the one or more deterministic outputs to detect a faulty emulation processor, a faulty emulation processor cluster, or a faulty emulation chip of the emulation system.

Abstract: A handling apparatus (14a) handles a server attack taking place on a network (1Na) or handles a server attack as requested by a security system provided on another network. In accordance with a determination that it is not possible to handle the server attack by the handling apparatus (14a), the control determination apparatus (12a) makes a request to another security system (1Sb) capable of handling the server attack to handle the server attack. A centralized control apparatus (11) determines whether the server attack taking place on the network (1Na) can be handled on another network.

Abstract: Disclosed herein are systems and methods of compiling resources of a programmable emulation system to execute an emulation process, to emulate a logic system, such as an application-specific integrated circuit (ASIC), currently being tested and prototyped, and then revising, transforming, and moving the compiled instructions sets to inexpensively, quickly, and dynamically adapt to unavailable resources, which may be due to previously allocation to a different emulation job, or for fault tolerance. Relocation of the resources that will execute the emulation job (i.e., “footprint”) may refer to the remapping of a compiled footprint to a revised set of resources, defining a revised footprint. Fault tolerance may refer to support for working around faulty hardware components of the emulation system.

Abstract: Disclosed herein are systems and methods to generate, by a compiling processor, one or more sets of one or more execution instructions responsive to compiling a netlist file. The method further includes storing, by the compiling processor, a set of execution instructions into an instruction memory of an execution processor. The method further includes generating, by a compiling processor, a set of one or more keephot instructions for the execution processor based upon the set of execution instructions stored into the instruction memory of the execution processor. The method further includes storing, by a compiling processor, the set of keephot instructions into the instruction memory of the execution processor.

Abstract: A control-circuit of an emulation system may include one or more serial link inputs communicatively coupled to a serial bus, a serial link input receiving an input control bit from the serial bus. A configurable logic circuit may be configured to receive multiple control bits from the one or more serial link inputs, execute one or more operations on the plurality of input control bits according to programmable logic, and transmit an output control bit to a serial output link.

Abstract: Disclosed herein are systems and methods to generate, by a compiling processor, one or more sets of one or more execution instructions responsive to compiling a netlist file. The method further includes storing, by the compiling processor, a set of execution instructions into an instruction memory of an execution processor. The method further includes generating, by a compiling processor, a set of one or more keephot instructions for the execution processor based upon the set of execution instructions stored into the instruction memory of the execution processor. The method further includes storing, by a compiling processor, the set of keephot instructions into the instruction memory of the execution processor.

Abstract: Systems and methods of emulating application-specific integrated circuits using multiple execution phases, where different inputs and outputs are used or produced by components of the emulation system are disclosed. For example, an OMUX may select and transmit different data over a serial bus based on the execution phase of the emulator system. In another example, a processor or cluster may capture outputted data during a first execution phase, execute instructions for a second execution phase, and then return to the capture outputted data for further processing during a next cycle of the first execution phase.

Abstract: In a system and method for emulating a circuit design, an emulation system receives input instructions from a host device executing the emulation. Channels of multiple buffers and associated processors provide implement read and write instructions received at the interface. Multiple access modes are provided to read and write to system memory and to store sequences of commands in the provided buffers and to execute those stored sequences using an associated processor. By writing a sequence of commands and/or data blocks to the channel buffers, the associated processors can execute programs of varying complexity that may have been written or modified in real time or preconfigured.