Patents by Inventor Yuhei Ikemoto

Yuhei Ikemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11355593
    Abstract: A semiconductor device comprises: a nitride semiconductor layer; an oxide insulating film formed to contact the nitride semiconductor layer; and a gate electrode formed to contact the oxide insulating film and made of metal nitride in a crystal orientation including at least one of the (200) orientation and the (220) orientation.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 7, 2022
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takatomi Izumi, Junya Nishii, Yuhei Ikemoto
  • Publication number: 20190103464
    Abstract: A semiconductor device comprises: a nitride semiconductor layer; an oxide insulating film formed to contact the nitride semiconductor layer; and a gate electrode formed to contact the oxide insulating film and made of metal nitride in a crystal orientation including at least one of the (200) orientation and the (220) orientation.
    Type: Application
    Filed: September 19, 2018
    Publication date: April 4, 2019
    Inventors: Takatomi Izumi, Junya Nishii, Yuhei Ikemoto
  • Patent number: 9117972
    Abstract: The light-emitting device has a semiconductor layer including a p-layer, a light-emitting layer, and an n-layer, which are formed of a Group III nitride semiconductor, and an n-electrode on the n-layer. The device also has a device isolation trench which runs along the outer periphery of the semiconductor layer and which provides the semiconductor layer with a mesa shape; and an insulation film continuously provided on first to third regions, the first region being an outer peripheral region of the n-layer, the second region being the side surface of the trench, and the third region being the bottom surface of the device isolation trench. The n-electrode consists of two pad portions and a wire trace portion. The outer peripheral wire trace portion is formed as a frame completely contouring the periphery of the device.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: August 25, 2015
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Koichi Mizutani, Ryohei Inazawa, Yuhei Ikemoto, Tomoyuki Tainaka
  • Patent number: 8735927
    Abstract: The invention provides a Group III nitride semiconductor light-emitting device which has a light extraction face at the n-layer side and which provides high light emission efficiency. The light-emitting device is produced through the laser lift-off technique. The surface of the n-GaN layer of the light-emitting device is roughened. On the n-GaN layer, a transparent film is formed. The transparent film satisfies the following relationship: 0.28?n×d1×2/??0.42 or 0.63?n×d1×2/??0.77, wherein n represents the refractive index of the transparent film, d1 represents the thickness of the transparent film in the direction orthogonal to an inclined face thereof, and ? represents the wavelength of the light emitted from the MQW layer.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: May 27, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yuhei Ikemoto, Naoki Arazoe
  • Publication number: 20110303938
    Abstract: A group III nitride semiconductor light-emitting element having improved light extraction efficiency is provided. The light-emitting element has a plurality of dot-like grooves formed on a surface at the side joining to a p-electrode of a p-type layer. The groove has a depth reaching an n-type layer. Side surface of the groove is slanted such that a cross-section in an element surface direction is decreased toward the n-type layer from the p-type layer. Fine irregularities are formed on the surface at the side joining to an n-electrode of the n-type layer, except for a region on which the n-electrode is formed, and a translucent insulating film having a refractive index of from 1.5 to 2.3 is formed on the fine irregularities. Light extraction efficiency is improved by reflection of light to the n-type layer side by the groove and prevention of reflection to the n-type layer side by the insulating film.
    Type: Application
    Filed: December 13, 2010
    Publication date: December 15, 2011
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Naoki Arazoe, Yuhei Ikemoto
  • Publication number: 20100270548
    Abstract: A semiconductor element includes a substrate including gallium oxide and having a predetermined plane direction, and a semiconductor layer formed on the substrate, in which, the semiconductor element is in chip form and further includes a first end face formed along a cleaved surface of the substrate and a second end face formed perpendicular to the first end face, wherein the first end face has a stronger cleavage property than the second end face.
    Type: Application
    Filed: July 6, 2010
    Publication date: October 28, 2010
    Inventors: Yuhei Ikemoto, Koji Hirata, Kazuo Aoki, Yukio Kaneko, Takekazu Ujiie
  • Patent number: 7576363
    Abstract: In a group III nitride compound semiconductor light emitting device comprising an n-type semiconductor layer, a p-type semiconductor layer having a superlattice structure in which a first layer comprising at least Al and a second layer having a different composition from that of the first layer are laminated repetitively, and an active layer interposed between the n-type semiconductor layer and the p-type semiconductor layer, wherein an Al composition of the first layer which is the closest to the active layer is set to be lower than that of each of the other first layers, and wherein a doping amount of a p-type impurity in the first layer which is the closest to the active layer is set to be smaller than that of the p-type impurity of each of the other first layers or non-doped.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: August 18, 2009
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Katsuhisa Sawazaki, Masahito Nakai, Yuhei Ikemoto
  • Patent number: 7572652
    Abstract: A light emitting element having a light emitting element portion formed of a group III nitride-based compound semiconductor and having a layer to emit light. The light emitting element portion is formed by lifting off a substrate by wet etching after the light emitting element portion is grown on the substrate. The light emitting element portion has a lift-off surface that is kept substantially intact as it is formed in growing the light emitting element portion on the substrate.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: August 11, 2009
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yuhei Ikemoto, Koji Hirata, Kazuhiro Ito, Yu Uchida, Susumu Tsukimoto, Masanori Murakami
  • Patent number: 7524741
    Abstract: A method of forming a low temperature-grown buffer layer having the steps of: placing a Ga2O3 substrate in a MOCVD apparatus; providing a H2 atmosphere in the MOCVD apparatus and setting a buffer layer growth condition having an atmosphere temperature of 350° C. to 550° C.; and supplying a source gas having two or more of TMG, TMA and NH3 onto the Ga2O3 substrate in the buffer layer growth condition to form the low temperature-grown buffer layer on the Ga2O3 substrate.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 28, 2009
    Assignees: Toyoda Gosei Co., Ltd., Koha Co., Ltd.
    Inventors: Yasuhisa Ushida, Daisuke Shinoda, Daisuke Yamazaki, Koji Hirata, Yuhei Ikemoto, Naoki Shibata, Kazuo Aoki, Encarnacion Antonia Garcia Villora, Kiyoshi Shimamura
  • Publication number: 20090001384
    Abstract: Provided is an HFET exhibiting reduced buffer leakage current. The HFET of the present invention includes an SiC substrate, an AlN layer, a graded AlGaN layer, a GaN layer, an AlGaN layer (Al compositional proportion: 20%), a source electrode, a gate electrode, and a drain electrode, wherein the AlN layer, the graded AlGaN layer, the GaN layer, and the AlGaN (Al: 20%) layer are successively stacked on the substrate, and the electrodes are formed on the AlGaN (Al: 20%) layer so as to be separated from one another. In the graded AlGaN layer, the Al compositional proportion gradually decreases from 30% (at the side facing the AlN layer) to 5% (at the side facing the GaN layer). Provision of the graded AlGaN layer reduces strain between the AlN layer and the GaN layer. Therefore, the HFET exhibits reduced buffer leakage current.
    Type: Application
    Filed: June 25, 2008
    Publication date: January 1, 2009
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Masayoshi Kosaki, Yuhei Ikemoto, Takahiro Sonoyama, Hiroshi Miwa
  • Publication number: 20070210320
    Abstract: A light emitting element having a light emitting element portion formed of a group III nitride-based compound semiconductor and having a layer to emit light. The light emitting element portion is formed by lifting off a substrate by wet etching after the light emitting element portion is grown on the substrate. The light emitting element portion has a lift-off surface that is kept substantially intact as it is formed in growing the light emitting element portion on the substrate.
    Type: Application
    Filed: February 21, 2007
    Publication date: September 13, 2007
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Yuhei Ikemoto, Koji Hirata, Kazuhiro Ito, Yu Uchida, Susumu Tsukimoto, Masanori Murakami
  • Publication number: 20070134833
    Abstract: A method of making a semiconductor element which has a substrate formed of gallium oxide and a semiconductor layer formed on the substrate. The method has: a first dividing step that the substrate with the semiconductor layer formed thereon is divided into a strip bar along a first cleaved surface of the substrate; and a second dividing step that the strip bar is divided in a direction perpendicular to the first cleaved surface.
    Type: Application
    Filed: December 11, 2006
    Publication date: June 14, 2007
    Applicants: TOYODA GOSEI CO., LTD., KOHA CO., LTD.
    Inventors: Yuhei Ikemoto, Koji Hirata, Kazuo Aoki, Yukio Kaneko, Takekazu Ujiie
  • Publication number: 20070131951
    Abstract: A light-emitting element having: a gallium oxide substrate on a front surface of which a crystal of a semiconductor material having a light-emitting element part is grown; and a substrate protection layer formed on a back surface of the gallium oxide substrate. A method of making a light-emitting element having the steps of: forming a substrate protection layer on a back surface of a gallium oxide substrate; growing a crystal of a semiconductor material having a light-emitting element part on a front surface of the gallium oxide substrate; and assembling the light-emitting element so as to form a electrical connection for the light-emitting element part.
    Type: Application
    Filed: December 6, 2006
    Publication date: June 14, 2007
    Applicants: TOYODA GOSEI CO., LTD., KOHA CO., LTD.
    Inventors: Yuhei Ikemoto, Koji Hirata, Kazuo Aoki
  • Publication number: 20060223287
    Abstract: A method of forming a low temperature-grown buffer layer having the steps of: placing a Ga2O3 substrate in a MOCVD apparatus; providing a H2 atmosphere in the MOCVD apparatus and setting a buffer layer growth condition having an atmosphere temperature of 350° C. to 550° C.; and supplying a source gas having two or more of TMG, TMA and NH3 onto the Ga2O3 substrate in the buffer layer growth condition to form the low temperature-grown buffer layer on the Ga2O3 substrate.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 5, 2006
    Applicants: Toyoda Gosei Co., Ltd, KOHA Co., Ltd.
    Inventors: Yasuhisa Ushida, Daisuke Shinoda, Daisuke Yamazaki, Koji Hirata, Yuhei Ikemoto, Naoki Shibata, Kazuo Aoki, Encarnacion Garcia Villora, Kiyoshi Shimamura
  • Publication number: 20060108603
    Abstract: In a group III nitride compound semiconductor light emitting device comprising an n-type semiconductor layer, a p-type semiconductor layer having a superlattice structure in which a first layer comprising at least Al and a second layer having a different composition from that of the first layer are laminated repetitively, and an active layer interposed between the n-type semiconductor layer and the p-type semiconductor layer, wherein an Al composition of the first layer which is the closest to the active layer is set to be lower than that of each of the other first layers, and wherein a doping amount of a p-type impurity in the first layer which is the closest to the active layer is set to be smaller than that of the p-type impurity of each of the other first layers or non-doped.
    Type: Application
    Filed: October 7, 2005
    Publication date: May 25, 2006
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Katsuhisa Sawazaki, Masahito Nakai, Yuhei Ikemoto