Abstract: A display device includes an organic EL element layer, a liquid crystal element layer disposed on top of the organic EL element layer, and a polarizing plate disposed at a side of the liquid crystal element layer that faces an observer. The liquid crystal element layer includes two transparent substrates and a liquid crystal layer disposed between the two transparent substrates. The liquid crystal element layer is configured to be able to, by applying a voltage to the liquid crystal layer, cause a substantially quarter-wavelength retardation in light passing through the liquid crystal layer.

Abstract: When binary pixel data is written to a pixel circuit, of an H-level (3V) and a L-level (0V), a voltage of the level indicating the binary pixel data is held at a first node, and a voltage of the inverted level thereof is held at a second node. The first and second nodes are connected to a third node via N-channel transistors, respectively, and first and second selection control signals are supplied to gate terminals of the transistors, respectively. Voltage levels of the first and second selection control signals are periodically switched between 5V indicating the H-level and 0V indicating the L-level in a mutually inverted manner. As a result, the voltage of the first node and the voltage of the second node are alternately selected and applied to a pixel electrode of a display element.

Abstract: A plurality of pixel electrodes are provided in a display region. A plurality of pixel transistors corresponding to the plurality of pixel electrodes in a one-to-one manner are provided in a region outside the display region. Each of the pixel transistors is connected to the corresponding pixel electrode by a pixel wiring line. An input pad group, to which a drive signal group for driving the plurality of pixel transistors is input, is provided on a TFT substrate. Here, of a region on the TFT substrate, the plurality of pixel transistors are provided only in a region other than a region between the input pad group and the display region.

Abstract: When binary pixel data is written to a pixel circuit, of an H-level (3V) and a L-level (0V), a voltage of the level indicating the binary pixel data is held at a first node, and a voltage of the inverted level thereof is held at a second node. The first and second nodes are connected to a third node via N-channel transistors, respectively, and first and second selection control signals are supplied to gate terminals of the transistors, respectively. Voltage levels of the first and second selection control signals are periodically switched between 5V indicating the H-level and 0V indicating the L-level in a mutually inverted manner. As a result, the voltage of the first node and the voltage of the second node are alternately selected and applied to a pixel electrode of a display element.

Abstract: A signal obtained through sampling a gate start pulse signal GSP by using one of a plurality of gate clock signals is supplied as a shift pulse for a forward shift action (a forward shift start pulse signal) to the first stage of a plurality of stages constituting a bidirectional shift register, and a signal obtained through sampling the gate start pulse signal GSP by using another one of the plurality of gate clock signals is supplied as a shift pulse for a backward shift action (a backward shift start pulse signal) to the last stage of the plurality of stages constituting the bidirectional shift register.

Abstract: A display device includes an organic EL element layer, a liquid crystal element layer disposed on top of the organic EL element layer, and a polarizing plate disposed at a side of the liquid crystal element layer that faces an observer. The liquid crystal element layer includes two transparent substrates and a liquid crystal layer disposed between the two transparent substrates. The liquid crystal element layer is configured to be able to, by applying a voltage to the liquid crystal layer, cause a substantially quarter-wavelength retardation in light passing through the liquid crystal layer.

Abstract: A plurality of pixel electrodes are provided in a display region. A plurality of pixel transistors corresponding to the plurality of pixel electrodes in a one-to-one manner are provided in a region outside the display region. Each of the pixel transistors is connected to the corresponding pixel electrode by a pixel wiring line. An input pad group, to which a drive signal group for driving the plurality of pixel transistors is input, is provided on a TFT substrate. Here, of a region on the TFT substrate, the plurality of pixel transistors are provided only in a region other than a region between the input pad group and the display region.

Abstract: A layout pattern of a demultiplexer circuit of a display device employing the SSD method is configured as described below. Specifically, demultiplexers in the demultiplexer circuit are grouped with three demultiplexers as one set, and nine transistors as switching elements included in the three demultiplexers of each set are arranged to be aligned in the extending direction of a source line with three transistors as a unit while positions of the nine transistors are sequentially shifted in the vertical direction with respect to the source line. Furthermore, any two adjacent sets are arranged such that a direction in which nine transistors included in one set are shifted in the vertical direction with three transistors as a unit and a direction in which nine transistors in the other set are shifted in the above-described vertical direction with three transistors as a unit are opposite to each other.

Abstract: A layout pattern of a demultiplexer circuit of a display device employing the SSD method is configured as described below. Specifically, demultiplexers in the demultiplexer circuit are grouped with three demultiplexers as one set, and nine transistors as switching elements included in the three demultiplexers of each set are arranged to be aligned in the extending direction of a source line with three transistors as a unit while positions of the nine transistors are sequentially shifted in the vertical direction with respect to the source line. Furthermore, any two adjacent sets are arranged such that a direction in which nine transistors included in one set are shifted in the vertical direction with three transistors as a unit and a direction in which nine transistors in the other set are shifted in the above-described vertical direction with three transistors as a unit are opposite to each other.

Abstract: A signal obtained through sampling a gate start pulse signal GSP by using one of a plurality of gate clock signals is supplied as a shift pulse for a forward shift action (a forward shift start pulse signal) to the first stage of a plurality of stages constituting a bidirectional shift register, and a signal obtained through sampling the gate start pulse signal GSP by using another one of the plurality of gate clock signals is supplied as a shift pulse for a backward shift action (a backward shift start pulse signal) to the last stage of the plurality of stages constituting the bidirectional shift register.

Abstract: A display device includes a pixel unit, a binary driver, and a timing generator. The display device is an active matrix display device configured to receive a data signal including image data and other data different from the image data. The pixel unit includes a memory configured to store the image data. The binary driver includes a first holding circuit configured to hold the image data and at least one second holding circuit configured to hold the other data. The timing generator is configured to generate a drive signal used for driving the binary driver.

Abstract: A layout pattern of a demultiplexer circuit of a display device employing the SSD method is configured as described below. Specifically, demultiplexers in the demultiplexer circuit are grouped with three demultiplexers as one set, and nine transistors as switching elements included in the three demultiplexers of each set are arranged to be aligned in the extending direction of a source line with three transistors as a unit while positions of the nine transistors are sequentially shifted in the vertical direction with respect to the source line. Furthermore, any two adjacent sets are arranged such that a direction in which nine transistors included in one set are shifted in the vertical direction with three transistors as a unit and a direction in which nine transistors in the other set are shifted in the above-described vertical direction with three transistors as a unit are opposite to each other.

Abstract: A layout pattern of a demultiplexer circuit of a display device employing the SSD method is configured as described below. Specifically, demultiplexers in the demultiplexer circuit are grouped with three demultiplexers as one set, and nine transistors as switching elements included in the three demultiplexers of each set are arranged to be aligned in the extending direction of a source line with three transistors as a unit while positions of the nine transistors are sequentially shifted in the vertical direction with respect to the source line. Furthermore, any two adjacent sets are arranged such that a direction in which nine transistors included in one set are shifted in the vertical direction with three transistors as a unit and a direction in which nine transistors in the other set are shifted in the above-described vertical direction with three transistors as a unit are opposite to each other.

Abstract: The display device includes, on a substrate, a plurality of pixel electrodes, M (M is a natural number equal to or greater than three) counter electrodes disposed opposite the plurality of pixel electrodes, M counter electrode wiring lines connected with M counter electrodes, and N (N is a natural number and 2?N<M) common voltage wiring lines connected to the M counter electrode wiring lines. Counter electrode wiring lines connected to counter electrodes adjacent to each other are connected to common voltage wiring lines that are different from each other.

Abstract: A display device includes a pixel unit, a binary driver, and a timing generator. The display device is an active matrix display device configured to receive a data signal including image data and other data different from the image data. The pixel unit includes a memory configured to store the image data. The binary driver includes a first holding circuit configured to hold the image data and at least one second holding circuit configured to hold the other data. The timing generator is configured to generate a drive signal used for driving the binary driver.

Abstract: A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.

Abstract: A decline in the display quality in portion areas corresponding to source lines that run through an inner non-display area in a display area is reduced. The arrangement of source lines that run through an inner non-display area is changed in an upper change area and a lower change area so that the source lines that are simultaneously driven are not adjacent to each other in a display area and are adjacent to each other in a passage area.

Abstract: A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.

Abstract: A decline in the display quality in portion areas corresponding to source lines that run through an inner non-display area in a display area is reduced. The arrangement of source lines that run through an inner non-display area changed in an upper change area and a lower change area so that the source lines that are simultaneously driven are not adjacent to each other in a display area and are adjacent to each other in a passage area.

Abstract: The display device includes, on a substrate, a plurality of pixel electrodes, M (M is a natural number equal to or greater than three) counter electrodes disposed opposite the plurality of pixel electrodes, M counter electrode wiring lines connected with M counter electrodes, and N (N is a natural number and 2?N<M) common voltage wiring lines connected to the M counter electrode wiring lines. Counter electrode wiring lines connected to counter electrodes adjacent to each other are connected to common voltage wiring lines that are different from each other.