Patents by Inventor Yuhki FUJINO
Yuhki FUJINO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942539Abstract: A semiconductor device includes a polycrystalline silicon part buried in a termination region of a silicon layer. The polycrystalline silicon part contacts the silicon layer, has a higher crystal grain density than the silicon layer, and includes a heavy metal. The silicon layer includes a drift layer located in a cell region and the termination region. The drift layer has a lower first-conductivity-type impurity concentration than a silicon substrate. The drift layer includes a same element of heavy metal as the heavy metal included in the polycrystalline silicon part.Type: GrantFiled: September 10, 2021Date of Patent: March 26, 2024Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Shotaro Baba, Hiroaki Katou, Yuhki Fujino, Kouta Tomita
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Publication number: 20240097023Abstract: A semiconductor device includes: a semiconductor part including a first semiconductor layer and a second semiconductor layer in contact with the first semiconductor layer; a first electrode electrically connected to the first semiconductor layer on a front surface side or a back surface side of the semiconductor part; a second electrode electrically connected to the second semiconductor layer on the front surface side of the semiconductor part; a gate electrode; an interlayer insulating film electrically insulating the gate electrode and the second electrode on the front surface side of the semiconductor part; and a third semiconductor layer having: a first region in contact with the second semiconductor layer and the second electrode on the front surface side of the semiconductor part; and a second region provided between the interlayer insulating film and the second electrode in a second direction perpendicular to a first direction.Type: ApplicationFiled: February 21, 2023Publication date: March 21, 2024Inventors: Yuhki FUJINO, Tsuyoshi KACHI, Katsura MIYASHITA, Shingo SATO
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Publication number: 20230307510Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions a plurality of conductive parts, and a gate electrode. The first semiconductor region is located on the first electrode and electrically connected with the first electrode. The conductive parts are located in the first semiconductor region with insulating parts interposed. The second semiconductor region is located on a portion of the first semiconductor region. The third semiconductor region is located on a portion of the second semiconductor region. The gate electrode is located on the second semiconductor region with a gate insulating layer interposed. The second electrode is located on the second and third semiconductor regions, and the gate electrode and electrically connected with the second and third semiconductor regions, and conductive parts.Type: ApplicationFiled: July 21, 2022Publication date: September 28, 2023Inventor: Yuhki FUJINO
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Patent number: 11769805Abstract: A semiconductor device includes: a first insulating film provided in a trench reaching a second semiconductor layer from above the second semiconductor region; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film; the second insulating film being provided between the side surface of the second electrode and a fifth insulating film provided between a side surface of the second electrode and the second semiconductor layer, the second insulating film containing a second insulating material having a higher dielectric constant than the first insulating material; a third electrode provided above the second electrode, the first insulating film and the second insulating film, the third electrode facing the first semiconductor region; an interlayer insulating film provided on the third electrode; and a fourth electrode provided above the interlayer insulating film.Type: GrantFiled: February 2, 2022Date of Patent: September 26, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventor: Yuhki Fujino
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Publication number: 20230290820Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode, and electrically connected to the first electrode. The second semiconductor region is provided on a part of the first semiconductor region. The third semiconductor region is provided on another part of the first semiconductor region. The third semiconductor region includes first and second regions. The fourth semiconductor region is provided on the second semiconductor region. The fifth semiconductor region is provided on a part of the fourth semiconductor region. The gate electrode faces the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region. The second electrode is provided on the fourth and fifth semiconductor regions. The second electrode is electrically connected to the fourth and fifth semiconductor regions.Type: ApplicationFiled: May 15, 2023Publication date: September 14, 2023Inventor: Yuhki Fujino
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Patent number: 11756791Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, fourth, and sixth semiconductor regions of a first conductivity type, a junction region, a fifth semiconductor region of a second conductivity type, and a gate electrode. The junction region includes a second semiconductor region of the first conductivity type and a third second semiconductor region of the second conductivity type. The second semiconductor regions and the third semiconductor regions are alternately provided in a second direction perpendicular to a first direction. A concentration of at least one first element selected from the group consisting of a heavy metal element and a proton in the junction region is greater a concentration of the first element in the fourth semiconductor region, or a density of traps in the junction region is greater than that in the first semiconductor region and greater than that in the fourth semiconductor region.Type: GrantFiled: September 10, 2020Date of Patent: September 12, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Shingo Sato, Yuhki Fujino, Hiroaki Yamashita
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Patent number: 11705334Abstract: A semiconductor device includes a semiconductor part; first and second electrodes, the semiconductor part being provided between the first and second electrodes; a control electrode selectively provided between the semiconductor part and the second electrode; and a contacting part electrically connecting the semiconductor part and the second electrode. The semiconductor part includes a first layer of a first conductivity type, a second layer of a second conductivity type provided between the first layer and the second electrode, a third layer of the first conductivity type selectively provided between the second layer and the second electrode, and a fourth layer of the second conductivity type selectively provided between the second layer and the second electrode. The contacting part includes a first semiconductor portion of the first conductivity type contacting the third layer, and a second semiconductor portion of the second conductivity type contacting the fourth layer.Type: GrantFiled: July 2, 2021Date of Patent: July 18, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Yuhki Fujino
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Patent number: 11688765Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode, and electrically connected to the first electrode. The second semiconductor region is provided on a part of the first semiconductor region. The third semiconductor region is provided on another part of the first semiconductor region. The third semiconductor region includes first and second regions. The fourth semiconductor region is provided on the second semiconductor region. The fifth semiconductor region is provided on a part of the fourth semiconductor region. The gate electrode faces the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region. The second electrode is provided on the fourth and fifth semiconductor regions. The second electrode is electrically connected to the fourth and fifth semiconductor regions.Type: GrantFiled: March 11, 2021Date of Patent: June 27, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Yuhki Fujino
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Publication number: 20220310837Abstract: A semiconductor device includes a polycrystalline silicon part buried in a termination region of a silicon layer. The polycrystalline silicon part contacts the silicon layer, has a higher crystal grain density than the silicon layer, and includes a heavy metal. The silicon layer includes a drift layer located in a cell region and the termination region. The drift layer has a lower first-conductivity-type impurity concentration than a silicon substrate. The drift layer includes a same element of heavy metal as the heavy metal included in the polycrystalline silicon part.Type: ApplicationFiled: September 10, 2021Publication date: September 29, 2022Inventors: Shotaro BABA, Hiroaki KATOU, Yuhki FUJINO, Kouta TOMITA
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Publication number: 20220157952Abstract: A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of first conductivity type provided on the first semiconductor region; a first insulating film provided in a trench reaching the second semiconductor layer from above the second semiconductor region via the second semiconductor region and the first semiconductor region, the first insulating film containing a first insulating material; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film; a second insulating film provided between a position of 40% of a height of the second electrode from a lower end of the second electrode and a position of an upper end of the second elType: ApplicationFiled: February 2, 2022Publication date: May 19, 2022Inventor: Yuhki Fujino
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Patent number: 11282929Abstract: A trench MOSFET with first and second electrodes and having first and second semiconductor layers of a first conductivity type, a semiconductor layer of the second conductivity type and a first and second semiconductor region of the first and second conductivity type respectively. A first insulating film and a second insulating film provided between a position of 40% of a height of the second electrode from a lower end of the second electrode and a position of an upper end of the second electrode. The second insulating film has a material with higher dielectric constant than a first insulating material of the first insulating film. The first insulating film disposed in the trench below 40% of the height of the second electrode only contains the first insulating material. A third electrode and interlayer insulating film provided on the second electrode, and a fourth electrode above the interlayer insulating film.Type: GrantFiled: August 27, 2020Date of Patent: March 22, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Yuhki Fujino
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Publication number: 20220085159Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode, and electrically connected to the first electrode. The second semiconductor region is provided on a part of the first semiconductor region, The third semiconductor region is provided on another part of the first semiconductor region. The third semiconductor region includes first and second regions. The fourth semiconductor region is provided on the second semiconductor region. The fifth semiconductor region is provided on a part of the fourth semiconductor region. The gate electrode faces the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region. The second electrode is provided on the fourth and fifth semiconductor regions. The second electrode is electrically connected to the fourth and fifth semiconductor regions.Type: ApplicationFiled: March 11, 2021Publication date: March 17, 2022Inventor: Yuhki Fujino
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Publication number: 20210343532Abstract: A semiconductor device includes a semiconductor part; first and second electrodes, the semiconductor part being provided between the first and second electrodes; a control electrode selectively provided between the semiconductor part and the second electrode; and a contacting part electrically connecting the semiconductor part and the second electrode. The semiconductor part includes a first layer of a first conductivity type, a second layer of a second conductivity type provided between the first layer and the second electrode, a third layer of the first conductivity type selectively provided between the second layer and the second electrode, and a fourth layer of the second conductivity type selectively provided between the second layer and the second electrode. The contacting part includes a first semiconductor portion of the first conductivity type contacting the third layer, and a second semiconductor portion of the second conductivity type contacting the fourth layer.Type: ApplicationFiled: July 2, 2021Publication date: November 4, 2021Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Yuhki FUJINO
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Publication number: 20210305049Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, fourth, and sixth semiconductor regions of a first conductivity type, a junction region, a fifth semiconductor region of a second conductivity type, and a gate electrode. The junction region includes a second semiconductor region of the first conductivity type and a third second semiconductor region of the second conductivity type. The second semiconductor regions and the third semiconductor regions are alternately provided in a second direction perpendicular to a first direction. A concentration of at least one first element selected from the group consisting of a heavy metal element and a proton in the junction region is greater a concentration of the first element in the fourth semiconductor region, or a density of traps in the junction region is greater than that in the first semiconductor region and greater than that in the fourth semiconductor region.Type: ApplicationFiled: September 10, 2020Publication date: September 30, 2021Inventors: Shingo Sato, Yuhki Fujino, Hiroaki Yamashita
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Publication number: 20210296454Abstract: A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of first conductivity type provided on the first semiconductor region; a first insulating film provided in a trench reaching the second semiconductor layer from above the second semiconductor region via the second semiconductor region and the first semiconductor region, the first insulating film containing a first insulating material; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film; a second insulating film provided between a position of 40% of a height of the second electrode from a lower end of the second electrode and a position of an upper end of the second elType: ApplicationFiled: August 27, 2020Publication date: September 23, 2021Inventor: Yuhki Fujino
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Patent number: 11081355Abstract: A semiconductor device includes a semiconductor part; first and second electrodes, the semiconductor part being provided between the first and second electrodes; a control electrode selectively provided between the semiconductor part and the second electrode; and a contacting part electrically connecting the semiconductor part and the second electrode. The semiconductor part includes a first layer of a first conductivity type, a second layer of a second conductivity type provided between the first layer and the second electrode, a third layer of the first conductivity type selectively provided between the second layer and the second electrode, and a fourth layer of the second conductivity type selectively provided between the second layer and the second electrode. The contacting part includes a first semiconductor portion of the first conductivity type contacting the third layer, and a second semiconductor portion of the second conductivity type contacting the fourth layer.Type: GrantFiled: February 4, 2020Date of Patent: August 3, 2021Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Yuhki Fujino
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Publication number: 20210043458Abstract: A semiconductor device includes a semiconductor part; first and second electrodes, the semiconductor part being provided between the first and second electrodes; a control electrode selectively provided between the semiconductor part and the second electrode; and a contacting part electrically connecting the semiconductor part and the second electrode. The semiconductor part includes a first layer of a first conductivity type, a second layer of a second conductivity type provided between the first layer and the second electrode, a third layer of the first conductivity type selectively provided between the second layer and the second electrode, and a fourth layer of the second conductivity type selectively provided between the second layer and the second electrode. The contacting part includes a first semiconductor portion of the first conductivity type contacting the third layer, and a second semiconductor portion of the second conductivity type contacting the fourth layer.Type: ApplicationFiled: February 4, 2020Publication date: February 11, 2021Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Yuhki FUJINO
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Patent number: 10431491Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a semiconductor layer having a first conductivity type on a semiconductor substrate, forming a trench in the semiconductor substrate and the semiconductor layer, forming a semiconductor film having a second conductivity type on an inner wall surface and a bottom surface of the trench, forming a first insulating film including silicon oxide on a side surface and a bottom surface of the semiconductor film, forming a second insulating film including silicon nitride on a side surface and a bottom surface of the first insulating film, and forming a third insulating film including silicon oxide on a side surface and a bottom surface of the second insulating film.Type: GrantFiled: January 22, 2018Date of Patent: October 1, 2019Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Yuhki Fujino, Noboru Yokoyama, Hideki Okumura
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Publication number: 20180342415Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a semiconductor layer having a first conductivity type on a semiconductor substrate, forming a trench in the semiconductor substrate and the semiconductor layer, forming a semiconductor film having a second conductivity type on an inner wall surface and a bottom surface of the trench, forming a first insulating film including silicon oxide on a side surface and a bottom surface of the semiconductor film, forming a second insulating film including silicon nitride on a side surface and a bottom surface of the first insulating film, and forming a third insulating film including silicon oxide on a side surface and a bottom surface of the second insulating film.Type: ApplicationFiled: January 22, 2018Publication date: November 29, 2018Inventors: Yuhki Fujino, Noboru Yokoyama, Hideki Okumura
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Publication number: 20180083128Abstract: In some embodiments, according to one aspect, a semiconductor device includes a first semiconductor region of a first conductivity type that extends in a first direction, a second semiconductor region of a second conductivity type that is disposed adjacent to the first semiconductor region, extending in a second direction intersecting with the first direction, and having a surface which defines a first void in the second semiconductor region, a first insulating layer that is provided on the surface of the second semiconductor region which defines the first void, a third semiconductor region of the second conductivity type that is provided on the second semiconductor region and has a carrier concentration of the second conductivity type higher than a carrier concentration of the second conductivity type of the second semiconductor region, a fourth semiconductor region of the first conductivity type that is provided on the third semiconductor region, a gate insulating layer provided on the third semiconductor rType: ApplicationFiled: March 1, 2017Publication date: March 22, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Noboru YOKOYAMA, Yuhki FUJINO