Patents by Inventor Yu-Hsun Wu

Yu-Hsun Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984375
    Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Chen, Yu-Ling Tsai, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
  • Patent number: 11984419
    Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Patent number: 11983052
    Abstract: A display device and a bezel thereof are provided. The display device includes a display panel and a bezel. The display panel has a first surface and a second surface. The first surface includes at least one pixel pad section, and the second surface includes at least one circuit pad section. The bezel includes a first surface connecting portion, a second surface connecting portion and at least one conductive wire. The edge of the display panel having the pixel pad section and the circuit pad section is accommodated between the first surface connecting portion and the second surface connecting portion. Each conductive wire has a first end and a second end. The first end is disposed on the first surface connecting portion and the second end is disposed on the second surface connecting portion. The part of the first connecting portion having the first end corresponds to the pixel pad section, and the part of the second connecting portion having the second end corresponds to the circuit pad section.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: May 14, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Fan Chen, Che-Chia Chang, Shang-Jie Wu, Yu-Chieh Kuo, Yi-Jung Chen, Yu-Hsun Chiu, Mei-Yi Li, He-Yi Cheng
  • Patent number: 11980076
    Abstract: A tiled display device includes two panels and two cover layers respectively disposed on the two panels. The two cover layers include a contact region. A top portion and a bottom portion of the contact region have a height H. One of the two cover layers has a thickness Tn. One of the two panels has a distance Xn between an upper surface of the one of the two panels and the bottom portion of the contact region. The one of the two panels is corresponding to the one of the two cover layers. The height H, the thickness Tn and the distance Xn satisfy the equation: 0<H/(Xn+Tn)<0.8.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: May 7, 2024
    Assignee: InnoLux Corporation
    Inventors: Ping-Hsun Tsai, Shih-Fu Liao, I-An Yao, Yu-Chun Hsu, Yung-Hsun Wu, Sheng-Nan Fan
  • Publication number: 20240139337
    Abstract: The present disclosure relates to a method for treating a cancer and/or cancer metastasis in a subject comprising administering to the subject irinotecan loaded in a mesoporous silica nanoparticle. The present disclosure also provides a conjugate comprising an agent loaded in a mesoporous silica nanoparticle (MSN) defining at least one pore and having at least one functional group on a sidewall of the at least one pore.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Cheng-Hsun WU, SI-HAN WU, YI-PING CHEN, RONG-LIN ZHANG, CHUNG-YUAN MOU, Yu-Tse LEE
  • Publication number: 20240133918
    Abstract: In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.
    Type: Application
    Filed: April 12, 2023
    Publication date: April 25, 2024
    Inventors: MAO-NAN CHANG, CHI-LUN LIU, HSUEH-LIANG CHOU, YI-SHAN WU, CHIAO-JUNG LIN, YU-HSUN HSUEH
  • Publication number: 20240071330
    Abstract: A display device includes a display panel. The display panel has a functional display area. The functional display area includes a plurality of display pixels and a plurality of light transmitting regions. The plurality of display pixels are around by the plurality of the light transmitting regions. A boundary between one of the plurality of display pixels and one of the plurality of light transmitting regions comprises an arc segment.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 29, 2024
    Applicant: Innolux Corporation
    Inventors: Chia-Hao Tsai, Ming-Jou Tai, Yi-Shiuan Cherng, Yu-Shih Tsou, You-Cheng Lu, Yung-Hsun Wu
  • Publication number: 20230324804
    Abstract: A method of forming an extreme ultraviolet (EUV) mask includes forming a multilayer Mo/Si stack comprising alternating stacked Mo and Si layers over a mask substrate; forming a ruthenium capping layer over the multilayer Mo/Si stack; doping the ruthenium capping layer with a halogen element, a pentavalent element, a hexavalent element or combinations thereof; forming an absorber layer over the ruthenium capping layer; and etching the absorber layer to form a pattern in the absorber layer.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tsung SHIH, Yu-Hsun WU, Bo-Tsun LIU, Tsung-Chuan LEE
  • Patent number: 11720025
    Abstract: A method of forming an extreme ultraviolet (EUV) mask includes forming a multilayer Mo/Si stack comprising alternating stacked Mo and Si layers over a mask substrate; forming a ruthenium capping layer over the multilayer Mo/Si stack; doping the ruthenium capping layer with a halogen element, a pentavalent element, a hexavalent element or combinations thereof; forming an absorber layer over the ruthenium capping layer; and etching the absorber layer to form a pattern in the absorber layer.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tsung Shih, Yu-Hsun Wu, Bo-Tsun Liu, Tsung-Chuan Lee
  • Patent number: 11480869
    Abstract: A photomask includes a substrate, a multilayer stack disposed over the substrate and configured to reflect a radiation, a capping layer over the multilayer stack, and an anti-reflective layer over the capping layer. The anti-reflective layer comprises a first pattern, wherein the first pattern exposes the capping layer and is configured as a printable feature. The photomask also includes an absorber spaced apart from the printable feature from a top-view perspective.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chien-Hung Lai, Hao-Ming Chang, Chia-Shih Lin, Hsuan-Wen Wang, Yu-Hsin Hsu, Chih-Tsung Shih, Yu-Hsun Wu
  • Publication number: 20220326598
    Abstract: A method of forming an extreme ultraviolet (EUV) mask includes forming a multilayer Mo/Si stack comprising alternating stacked Mo and Si layers over a mask substrate; forming a ruthenium capping layer over the multilayer Mo/Si stack; doping the ruthenium capping layer with a halogen element, a pentavalent element, a hexavalent element or combinations thereof; forming an absorber layer over the ruthenium capping layer; and etching the absorber layer to form a pattern in the absorber layer.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 13, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tsung SHIH, Yu-Hsun WU, Bo-Tsun LIU, Tsung-Chuan LEE
  • Patent number: 11392022
    Abstract: A method of forming an extreme ultraviolet (EUV) mask includes forming a multilayer Mo/Si stack comprising alternating stacked Mo and Si layers over a mask substrate; forming a ruthenium capping layer over the multilayer Mo/Si stack; doping the ruthenium capping layer with a halogen element, a pentavalent element, a hexavalent element or combinations thereof; forming an absorber layer over the ruthenium capping layer; and etching the absorber layer to form a pattern in the absorber layer.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tsung Shih, Yu-Hsun Wu, Bo-Tsun Liu, Tsung-Chuan Lee
  • Publication number: 20220114303
    Abstract: A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.
    Type: Application
    Filed: December 24, 2020
    Publication date: April 14, 2022
    Inventors: CHUN-AN LIN, WEN-CHE SHEN, CHIH-WEI YEH, PO-HUAN CHOU, CHUN-CHIEH CHANG, YU-HSUN WU
  • Publication number: 20210389661
    Abstract: A method of forming an extreme ultraviolet (EUV) mask includes forming a multilayer Mo/Si stack comprising alternating stacked Mo and Si layers over a mask substrate; forming a ruthenium capping layer over the multilayer Mo/Si stack; doping the ruthenium capping layer with a halogen element, a pentavalent element, a hexavalent element or combinations thereof; forming an absorber layer over the ruthenium capping layer; and etching the absorber layer to form a pattern in the absorber layer.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tsung SHIH, Yu-Hsun WU, Bo-Tsun LIU, Tsung-Chuan LEE
  • Publication number: 20210063869
    Abstract: A photomask includes a substrate, a multilayer stack disposed over the substrate and configured to reflect a radiation, a capping layer over the multilayer stack, and an anti-reflective layer over the capping layer. The anti-reflective layer comprises a first pattern, wherein the first pattern exposes the capping layer and is configured as a printable feature. The photomask also includes an absorber spaced apart from the printable feature from a top-view perspective.
    Type: Application
    Filed: April 15, 2020
    Publication date: March 4, 2021
    Inventors: CHIEN-HUNG LAI, HAO-MING CHANG, CHIA-SHIH LIN, HSUAN-WEN WANG, YU-HSIN HSU, CHIH-TSUNG SHIH, YU-HSUN WU
  • Patent number: 10804761
    Abstract: The present disclosure provides a rotor mechanism includes a rotor core and a plurality of rotor bars. The rotor core has a plurality of insertion slots arranged along an edge of the rotor core. Each of the plurality of rotor bars has an insertion portion and two protruding portions. The insertion portions are respectively located in the plurality of insertion slots, wherein in each of the plurality of rotor bars, the two protruding portions are respectively connected to two opposite ends of the insertion portion and respectively protrude from two opposite sides of the rotor core, and the two protruding portions each has an extension direction, that has an angle with respect to an extension direction of the insertion portion, in order to clamp and fix the rotor core therebetween. In addition, the present disclosure also provides a method for manufacturing the rotor mechanism.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: October 13, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Hsun Wu, Ming-Mao Hsu, Yu-Yuan Chen
  • Publication number: 20190140506
    Abstract: The present disclosure provides a rotor mechanism includes a rotor core and a plurality of rotor bars. The rotor core has a plurality of insertion slots arranged along an edge of the rotor core. Each of the plurality of rotor bars has an insertion portion and two protruding portions. The insertion portions are respectively located in the plurality of insertion slots, wherein in each of the plurality of rotor bars, the two protruding portions are respectively connected to two opposite ends of the insertion portion and respectively protrude from two opposite sides of the rotor core, and the two protruding portions each has an extension direction, that has an angle with respect to an extension direction of the insertion portion, in order to clamp and fix the rotor core therebetween. In addition, the present disclosure also provides a method for manufacturing the rotor mechanism.
    Type: Application
    Filed: December 4, 2017
    Publication date: May 9, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Hsun Wu, Ming-Mao Hsu, Yu-Yuan Chen
  • Patent number: 10199894
    Abstract: A rotor of an electric motor including a rotor core, two conductive end plates, a plurality of conductors and a casting metal is provided. The rotor core has a central hole and a plurality of slots surrounding the central hole at a predetermined interval. The two conductive end plates, disposed at two ends of the rotor core, have a plurality of fixing structures, respectively. A plurality of cavities is disposed between two neighboring fixing structures and the shape and the positions of the cavities correspond to that of the slots. The conductors are shaped as long bars and penetrate the slots. Two ends of the conductors are fixed by the fixing structures. The casting metal is injected into the cavities and the slots, and further covers the peripheral of the conductors and the fixing structures, two ends of the rotor core and outside of the two conductive end plates.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 5, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: I-Wei Lan, Yu-Hsun Wu, Yee-Pien Yang
  • Publication number: 20170163111
    Abstract: A rotor of an electric motor including a rotor core, two conductive end plates, a plurality of conductors and a casting metal is provided. The rotor core has a central hole and a plurality of slots surrounding the central hole at a predetermined interval. The two conductive end plates, disposed at two ends of the rotor core, have a plurality of fixing structures, respectively. A plurality of cavities is disposed between two neighboring fixing structures and the shape and the positions of the cavities correspond to that of the slots. The conductors are shaped as long bars and penetrate the slots. Two ends of the conductors are fixed by the fixing structures. The casting metal is injected into the cavities and the slots, and further covers the peripheral of the conductors and the fixing structures, two ends of the rotor core and outside of the two conductive end plates.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 8, 2017
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: I-Wei LAN, Yu-Hsun WU, Yee-Pien YANG
  • Publication number: 20170047805
    Abstract: The disclosure provides a stator module and a magnetic field generating structure which includes a magnetizer and an electrically conducting pipe. The electrically conducting pipe is wound around the magnetizer and has a passage inside. The passage has an outlet and an inlet opposite to each other. The electrically conducting pipe has a current input portion and a current output portion.
    Type: Application
    Filed: October 24, 2016
    Publication date: February 16, 2017
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Se-Kang HO, Kuo-Lin CHIU, Chia-Min TING, Cheng-Min CHANG, Chen-Chih LIN, Hsien-Chang HUANG, Yu-Hsun WU