Abstract: Disclosed are a method and a system for processing public sentiment data, computer storage medium and an electronic device. The system includes: a network data integration platform configured to audit and analyze collected network public sentiment to acquire a sensitivity level of the network public sentiment, and send the network public sentiment and the sensitivity level of the network public sentiment to a big data cluster; the big data cluster configured to send the filtered network public sentiment to a business data integration platform; the business data integration platform configured to screen enterprise public sentiment from the filtered network public sentiment, and store an association relationship among the enterprise public sentiment, an acquired user account level and a sensitivity level of the enterprise public sentiment to a database server; and a data exhibition platform configured to exhibit the enterprise public sentiment with the target sensitivity level to an authenticated user.

Abstract: A redundant circuit assigning method includes: executing a first test item to obtain first test data including position data of fail bits acquired during execution of the first test item; determining a first redundant circuit assigning result according to the first test data, where the first redundant circuit assigning result includes a number of assigned local redundant circuits and their corresponding position data; executing a second test item to obtain second test data including position data of fail bits acquired during execution of the second test item; and determining a second redundant circuit assigning result according to the first test data and the second test data, when the fail bits acquired during the execution of the second test item include one or more fail bits beyond a repair range of the assigned local redundant circuits and assigned global redundant circuits and when assignable local redundant circuits have been assigned.

Abstract: Provided are a wafer defect tracing method and apparatus, an electronic device and a computer readable medium. The method includes: obtaining defect data of a wafer; obtaining position data of fail bits of the wafer; determining a defect area of a storage block in the wafer according to the defect data; determining a fail bit count of the storage block in the wafer according to the position data of the fail bits; processing the defect area and the fail bit count of each storage block in the wafer, so as to obtain a correlation coefficient; and determining an abnormal reason for the fail bits of the wafer according to the correlation coefficient.

Abstract: A Fail Bit (FB) repair method and device can be applied to repairing an FB in a chip. The method includes: a bank to be repaired including multiple target repair regions in a chip to be repaired is determined; first repair processing is performed on a first FB in each target repair region by using a redundant circuit; a second FB position determination step is executed to determine a bit position of a second FB, and second repair processing is performed on the second FB; unrepaired FBs in each target repair region is determined, and the second FB position determination step is recursively executed to obtain a test repair position of each unrepaired FB to perform third repair processing on the unrepaired FB according to the test repair position.

Abstract: A redundant circuit assigning method a includes: first test item is executed and first test data is acquired; a first redundant circuit assigning result including the number of assigned local redundant circuits and position data of the assigned local redundant circuits is determined according to the first test data; a second test item is executed and second test data is acquired; when fail bits acquired during execution of the second test item include one or more fail bits beyond the repair range of the assigned local redundant circuits and assigned global redundant circuits, and the assignable redundant circuits have been assigned out, target position data of fail bits in a target subdomain and a related subdomain is acquired based on the first test data and the second test data; and a second redundant circuit assigning result is determined according to the first test data and the second test data.

Abstract: A method for chip collection and a method for chip positioning are provided. The method for chip collection includes that: an image to be detected is obtained; chip position information of a comparison image with a highest matching degree with the image to be detected is obtained from a database; a position of each of detection regions in the image to be detected is obtained based on the chip position information; an image of the detection region is obtained based on the position of each detection region; it is determined whether the image of the detection region includes the chip code image; and when the image of the detection region includes the chip code image, a chip code corresponding to the chip code image identified and the chip code is stored in the database.

Abstract: A local region to be repaired including the fail bit is determined. A preliminary repair LR circuit for repairing the local region to be repaired is determined (S210). A region level of the local region to be repaired is determined (S230) according to the number of available GR circuits other than any replacement GR circuit configured for replacing the preliminary repair LR circuit and the number of available LR circuits. It is controlled, according to the region level of the local region to be repaired, to repair the fail bit by the GR circuit or the LR circuit (S240).

Abstract: A Fail Bit (FB) repair method includes: a bank to be repaired of a chip to be repaired is determined; first repair processing is performed on a first FB using a redundant circuit; a bit position of a second FB in each target repair bank is determined, and second repair processing is performed on the second FB; an unrepaired FB in each target repair bank is determined, and candidate repair combinations of the unrepaired FBs and a candidate combination count are determined; and if the candidate combination count is greater than a combination count threshold, a target repair position is determined, and repair processing is performed on the target repair position using a Redundant Word-Line (RWL), the target repair position being a position of an FB that maximally reduces the candidate combination count after repair processing.

Abstract: A method and an apparatus for determining a repair location for a redundancy circuit, and a method for repairing an integrated circuit are provided. At least one fail bit of a chip to be repaired is determined. At least one initial repair location for the redundancy circuit is initially assigned according to the at least one fail bit. At least one potential fail line is determined according to the at least one initial repair location. At least one predicted repair location is determined according to the at least one potential fail line. Each of the at least one predicted repair location is a location with a higher probability that a new fail bit appears. At least one final repair location for the redundancy circuit is determined according to the at least one fail bit and the at least one predicted repair location.

Abstract: A processing method of chip probing data includes: determining a new fail bit generated in an already completed chip probing process; acquiring repair record of the new fail bit, and repair records of bits adjacent to the new fail bit; analyzing the repair records to determine attribute information of the new fail bit and the adjacent bits, the attribute information including at least one of address information, redundant circuit information, element pattern of the new fail bit and chip probing flow; performing classification learning according to the attribute information to acquire a fail bit prediction model; and predicting fail bits to be chip-probed through the fail bit prediction model.

Abstract: A method for determining a Fail Bit (FB) repair scheme includes: a bank to be repaired of a chip to be repaired is determined, the bank to be repaired including multiple target repair areas; initial repair processing is performed on an FB in each of the target repair areas using a redundant circuit; responsive to that a number of remaining Redundant Word Lines (RWLs) is greater than 0 and a number of remaining Redundant Bit Lines (RBLs) is greater than 0, a candidate repair sub-scheme for each target repair area is determined, and a candidate repair cost corresponding to each candidate repair sub-scheme is determined; and a target repair scheme for the bank to be repaired is determined according to respective candidate repair sub-schemes and candidate repair costs, where the target repair scheme corresponds to a minimum integrated repair cost.

Abstract: Provided are standby circuit dispatch method, apparatus, device and medium. The method includes: a first test item is executed and first test data is acquired, the first test data including position data of a failure bit acquired during execution of the first test item; a first redundant circuit dispatch result is determined according to the first test data; a second test item is executed and second test data is acquired; when the failure bit acquired during execution of the second test item includes a failure bit outside the repair range of the dispatched regional redundant circuits and dispatched global redundant circuits, and the dispatchable redundant circuits have been dispatched out, a maximum target bit umber is acquired according to the first test data and the second test data; and a target dispatch mode is selected and a second redundant circuit dispatch result is determined according to the target dispatch mode.

Abstract: A method and device for Fail Bit (FB) repairing. The method includes: a bank to be repaired of a chip to be repaired is determined; first repair processing is performed on first FBs in each target repair bank using a redundant circuit; second FBs are determined, and second repair processing is performed on the second FBs through a state judgment repair operation; for each target repair bank, unrepaired FBs in the target repair bank is determined, and candidate repair combinations and candidate repair costs of the unrepaired FBs are determined using an optimal combined detection manner; and a target repair cost is determined according to the candidate repair costs, and a target repair solution corresponding to the target repair cost is determined to perform repair processing on the unrepaired FBs according to the target repair solution.

Abstract: Provided are a Fail Bit (FB) repair solution determination method and device, which are applied to a chip including multiple subdomains. The chip further includes Redundancy (RD) circuits, and the RD circuits are configured to repair FBs in the subdomains. The method includes that: after one or more available RD circuits are determined for a target FB presently to be repaired in a subdomain, a reliability value of each available RD circuit is acquired from an RD circuit reliability list, the RD circuit reliability list including reliability values of multiple RD circuits, and a repair solution for the target FB in the subdomain is determined according to the reliability value of the available RD circuit. The reliability value of the RD circuit is obtained by performing big data analysis on relationships between generated FBs and RD circuits where NFBs are located in the RD circuits.

Abstract: The present application discloses an acceptability check method and check system for detection tools. The check method includes: detecting a plurality of wafers using a detection tool to be checked, to obtain first detection data; detecting the plurality of wafers using an existing detection tool, to obtain second detection data; performing data analysis on the first detection data and the second detection data to obtain category classifications corresponding to the first detection data and the second detection data; and determining whether the first detection data corresponding to the category classification is acceptable; wherein the number of wafers detected using the detection tool to be checked and the number of wafers detected using the existing detection tool are the same.

Abstract: A method for chip collection and a method for chip positioning are provided. The method for chip collection includes that: an image to be detected is obtained; chip position information of a comparison image with a highest matching degree with the image to be detected is obtained from a database; a position of each of detection regions in the image to be detected is obtained based on the chip position information; an image of the detection region is obtained based on the position of each detection region; it is determined whether the image of the detection region includes the chip code image; and when the image of the detection region includes the chip code image, a chip code corresponding to the chip code image identified and the chip code is stored in the database.

Abstract: Embodiments provide a method and an apparatus for repairing a fail location. When repairing a fail location of a wafer, a fail bit in a wafer to be processed may be first determined, and a target potential fail bit associated with the fail bit may be determined based on a potential mining rule included in a mining rule library.

Abstract: A redundant circuit assigning method a includes: first test item is executed and first test data is acquired; a first redundant circuit assigning result including the number of assigned local redundant circuits and position data of the assigned local redundant circuits is determined according to the first test data; a second test item is executed and second test data is acquired; when fail bits acquired during execution of the second test item include one or more fail bits beyond the repair range of the assigned local redundant circuits and assigned global redundant circuits, and the assignable redundant circuits have been assigned out, target position data of fail bits in a target subdomain and a related subdomain is acquired based on the first test data and the second test data; and a second redundant circuit assigning result is determined according to the first test data and the second test data.

Abstract: Provided are standby circuit dispatch method, apparatus, device and medium. The method includes: a first test item is executed and first test data is acquired, the first test data including position data of a failure bit acquired during execution of the first test item; a first redundant circuit dispatch result is determined according to the first test data; a second test item is executed and second test data is acquired; when the failure bit acquired during execution of the second test item includes a failure bit outside the repair range of the dispatched regional redundant circuits and dispatched global redundant circuits, and the dispatchable redundant circuits have been dispatched out, a maximum target bit umber is acquired according to the first test data and the second test data; and a target dispatch mode is selected and a second redundant circuit dispatch result is determined according to the target dispatch mode.

Abstract: Embodiments of the present application are applied in the field of semiconductor inspection, and provide an acquisition apparatus, an acquisition system and an acquisition method. The acquisition apparatus includes: a base and a core plate, the core plate being configurated to carry a chip tray; a first support portion, being disposed on the base and connected with a first camera assembly, and the first camera assembly being disposed above the core plate; and a second support portion, being disposed on the base and connected with a second camera assembly, and the second camera assembly being disposed above the core plate; wherein the first camera assembly is configurated to capture an image of a first region of the chip tray, the second camera assembly is configurated to capture an image of a second region of the chip tray.