Abstract: A method of manufacturing a laminated core includes inserting permanent magnets 14 into magnet insertion holes 12, 12a of a core body 13; injecting a resin 18 into the holes 12, 12a from resin reservoir pots 17 in the die 15 (16) to fix the magnets 14; placing a dummy plate 19 between the die 15 having the pots 17 and the body 13, the plate 19 having gate holes 35, 35a guiding the resin 18 from the pots 17 into the holes 12, 12a, the hole 35 (35a) overlapping with both of a part of the hole 12 (12a) and a surface of the body 13; poring the resin 18 via the holes 35, 35a and curing the resin 18 in the holes 12, 12a; and separating the plate 19 from the body 13 to remove the resin 18 overflowed from the holes 12, 12a.

Abstract: A control apparatus 13 outputs an order signal to order supply apparatuses 12-1 through 12-N to perform supply of a signal in a contactless manner at a respectively different timing. The control apparatus 13 determines that a moving apparatus 11 is stopped at the position of the supply apparatus 12 being the output destination of the signal output order, when a wireless signal is received from the moving apparatus 11 within a certain period of time after outputting the order signal. Then, the supply apparatus 12 at the position at which the moving apparatus 11 is ordered to start supplying a signal.

Abstract: Disclosed herein is a synchronization circuit including: a first phase-locked loop circuit; a second phase-locked loop circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; and a control circuit.

Abstract: Disclosed herein is a signal processing device including an adjustment section configured to adjust the power of each of subinterval signals by multiplying the subinterval signals by a gain adapted to bring the power to a given level, the subinterval signals being input signals each having a frequency component of one of a plurality of subintervals into which the frequency band over which the power spectrum is to be measured is divided, and a correction section configured to correct the power of each of the subinterval signals, whose power has been adjusted by the adjustment section, by multiplying the power spectrum by the reciprocal of the gain used for adjustment of the power by the adjustment section.

Abstract: A receiving device includes: a noise detecting means for detecting a noise, which is contained in a received signal, using the received signal which has undergone clock synchronization processing: a phase error detecting means for detecting a phase error of the received signal using the received signal which has undergone clock synchronization processing; and a calculation means for calculating a phase correction value on the basis of the phase error detected by the phase error detecting means, wherein, when the noise is detected by the noise detecting means, the calculation means modifies a parameter to be employed in the calculation of the phase correction value so as to decrease the phase correction value.

Abstract: A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.

Abstract: Disclosed herein is a carrier synchronizing circuit including at least frequency synchronizing means and phase synchronizing means. The phase synchronizing means includes residual frequency error detecting means for detecting a residual frequency error after a frequency synchronizing process by the frequency synchronizing means and supplying the residual frequency error to the frequency synchronizing means, and the frequency synchronizing means performs frequency pull-in for the residual frequency error supplied from the residual frequency error detecting means after first timing.

Abstract: A charging device for a vehicle includes a device-side power line communication (PLC) modem, a device-side control pilot (CPLT) signal generating circuit, a device-side CPLT signal detecting circuit and a device-side low-pass filter (LPF). The device-side PLC modem is used for PLC between the vehicle and the charging device. The device-side CPLT signal generating circuit is used for generating CPLT signals. The device-side CPLT signal detecting circuit is used for detecting the CPLT signals transmitted from the vehicle through the signal line to determine whether or not the vehicle is ready for charging and whether or not the charging is completed. The device-side LPF is connected to an input of the device-side CPLT signal detecting circuit and has such a frequency characteristics that allows the CPLT signals to pass through the device-side LPF but removes signals having frequencies in a frequency band used for PLC.

Abstract: Disclosed herein is a signal processing device including an adjustment section configured to adjust the power of each of subinterval signals by multiplying the subinterval signals by a gain adapted to bring the power to a given level, the subinterval signals being input signals each having a frequency component of one of a plurality of subintervals into which the frequency band over which the power spectrum is to be measured is divided, and a correction section configured to correct the power of each of the subinterval signals, whose power has been adjusted by the adjustment section, by multiplying the power spectrum by the reciprocal of the gain used for adjustment of the power by the adjustment section.

Abstract: Disclosed herein is a synchronization circuit including: a first phase-locked loop circuit; a second phase-locked loop circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; and a control circuit.

Abstract: A receiving device includes: a noise detecting means for detecting a noise, which is contained in a received signal, using the received signal which has undergone clock synchronization processing: a phase error detecting means for detecting a phase error of the received signal using the received signal which has undergone clock synchronization processing; and a calculation means for calculating a phase correction value on the basis of the phase error detected by the phase error detecting means, wherein, when the noise is detected by the noise detecting means, the calculation means modifies a parameter to be employed in the calculation of the phase correction value so as to decrease the phase correction value.

Abstract: A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.

Abstract: Disclosed herein is a carrier synchronizing circuit including at least frequency synchronizing means and phase synchronizing means. The phase synchronizing means includes residual frequency error detecting means for detecting a residual frequency error after a frequency synchronizing process by the frequency synchronizing means and supplying the residual frequency error to the frequency synchronizing means, and the frequency synchronizing means performs frequency pull-in for the residual frequency error supplied from the residual frequency error detecting means after first timing.