Patents by Inventor Yuichi Mikata
Yuichi Mikata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7344805Abstract: A mask is provided wherein the mask has: a plate-like member having a mask pattern area and at least one pn junction; and a current supplying area which supplies a current to the pn junction, and a Peltier effect is caused by supplying a current to the pn junction, thereby enabling the temperature of the mask pattern area to be controlled. When this mask is used, reliable formation of an ion implanted region is enabled without forming a resist pattern.Type: GrantFiled: December 18, 2003Date of Patent: March 18, 2008Assignees: Rohm Co., Ltd., Toshiba CorporationInventors: Hiroshi Kumano, Yuichi Mikata
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Patent number: 6383897Abstract: In a method of producing a semiconductor apparatus, when a thin film is formed on a semiconductor substrate in the CVD reactive chamber by the CVD method, a remaining region is provided where a gas for film formation remains to a proximity of a surface of the semiconductor substrate, and a CVD thin film is provided on the substrate by decomposing only the gas for film formation existing in the remaining region without supplying an additional gas from the outside of the remaining region to the remaining region. With the method, when the thin film is formed on the substrate by the CVD method, the thin film is efficiently deposited on the substrate in a reactive chamber by efficiently using a reactive gas for film formation introduced into a CVD reactive chamber, to thereby reduce cost of forming the thin film remarkably.Type: GrantFiled: January 26, 2001Date of Patent: May 7, 2002Assignee: Kabushiki Kaisha ToshibaInventor: Yuichi Mikata
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Publication number: 20010012697Abstract: In a method of producing a semiconductor apparatus, when a thin film is formed on a semiconductor substrate in the CVD reactive chamber by the CVD method, a remaining region is provided where a gas for film formation remains to a proximity of a surface of the semiconductor substrate, and a CVD thin film is provided on the substrate by decomposing only the gas for film formation existing in the remaining region without supplying an additional gas from the outside of the remaining region to the remaining region. With the method, when the thin film is formed on the substrate by the CVD method, the thin film is efficiently deposited on the substrate in a reactive chamber by efficiently using a reactive gas for film formation introduced into a CVD reactive chamber, to thereby reduce cost of forming the thin film remarkably.Type: ApplicationFiled: January 26, 2001Publication date: August 9, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yuichi Mikata
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Patent number: 6211081Abstract: In a method of producing a semiconductor apparatus, when a thin film is formed on a semiconductor substrate in the CVD reactive chamber by the CVD method, a remaining region is provided where a gas for film formation remains to a proximity of a surface of the semiconductor substrate, and a CVD thin film is provided on the substrate by decomposing only the gas for film formation existing in the remaining region without supplying an additional gas from the outside of the remaining region to the remaining region. With the method, when the thin film is formed on the substrate by the CVD method, the thin film is efficiently deposited on the substrate in a reactive chamber by efficiently using a reactive gas for film formation introduced into a CVD reactive chamber, to thereby reduce cost of forming the thin film remarkably.Type: GrantFiled: March 27, 1997Date of Patent: April 3, 2001Assignee: Kabushiki Kaisha ToshibaInventor: Yuichi Mikata
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Patent number: 6188838Abstract: A susceptor in a semiconductor wafer heat treatment apparatus holds a wafer such that the wafer is made flat at a heat treatment temperature. In particular, the susceptor is constituted by an elastic platy member which is convex upward with respect to the direction of the gravity. Therefore, when the wafer is subjected to a high-temperature heat treatment, a crystal defect in the wafer can be suppressed.Type: GrantFiled: February 2, 1999Date of Patent: February 13, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Yuichi Mikata, Akihito Yamamoto
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Patent number: 5893760Abstract: A susceptor in a semiconductor wafer heat treatment apparatus holds a wafer such that the wafer is made flat at a heat treatment temperature. In particular, the susceptor is constituted by an elastic platy member which is convex upward with respect to the direction of the gravity. Therefore, when the wafer is subjected to a high-temperature heat treatment, a crystal defect in the wafer can be suppressed.Type: GrantFiled: March 26, 1997Date of Patent: April 13, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Yuichi Mikata, Akihito Yamamoto
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Patent number: 5750436Abstract: An Si.sub.3 N.sub.4 layer is formed on a surface of a wafer, which is an object to be processed, at a high temperature of, for example, 780.degree. C., using a vertical thermal processing apparatus having a reaction tube of a double-wall structure comprising an inner tube and an outer tube in which a predetermined reduced-pressure status is maintained within the reaction tube while a reaction gas comprising, for example, SiH.sub.2 Cl.sub.2 and NH.sub.3 is made to flow from an inner side to an outer side of the inner tube by the action of a first gas supply pipe and first exhaust pipe provided in the thermal processing apparatus. Next, the temperature in the interior of the reaction tube is raised to, for example, 1000.degree. C., a reaction gas comprising, for example, H.sub.2 O vapor and HCl is made to flow from the outer side to the inner side of the inner tube by the action of a second gas supply pipe and second exhaust pipe, and an SiO.sub.2 layer is formed by the oxidation of the surface of the Si.sub.Type: GrantFiled: June 7, 1995Date of Patent: May 12, 1998Assignees: Tokyo Electron Kabushiki Kaisha, Tokyo Electron Tohoku Kabushiki Kaisha, Kabushiki Kaisha ToshibaInventors: Kenichi Yamaga, Yuichi Mikata, Akihito Yamamoto
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Patent number: 5484484Abstract: An Si.sub.3 N.sub.4 layer is formed on a surface of a wafer, which is an object to be processed, at a high temperature of, for example, 780.degree. C., using a vertical thermal processing apparatus having a reaction tube of a double-wall structure comprising an inner tube and an outer tube in which a predetermined reduced-pressure status is maintained within the reaction tube while a reaction gas comprising, for example, SiH.sub.2 Cl.sub.2 and NH.sub.3 is made to flow from an inner side to an outer side of the inner tube by the action of a first gas supply pipe and first exhaust pipe provided in the thermal processing apparatus. Next, the temperature in the interior of the reaction tube is raised to, for example, 1000.degree. C., a reaction gas comprising, for example, H.sub.2 O vapor and HCl is made to flow from the outer side to the inner side of the inner tube by the action of a second gas supply pipe and second exhaust pipe, and an SiO.sub.2 layer is formed by the oxidation of the surface of the Si.sub.Type: GrantFiled: June 30, 1994Date of Patent: January 16, 1996Assignees: Tokyo Electron Kabushiki, Tokyo Electron Kabushiki Kaisha, Kabushiki Kaisha ToshibaInventors: Kenichi Yamaga, Yuichi Mikata, Akihito Yamamoto
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Patent number: 5252133Abstract: A vertically oriented CVD apparatus comprises a reaction chamber, a boat means vertically placed in the reaction chamber to horizontally support a plurality of semiconductor substrates, and a gas inlet tube including a plurality of gas injection holes along a longitudinal axis thereof and extending along a longitudinal side of the boat means to introduce a reaction gas into the reaction chamber. In the structure, a direction of each of the gas injection holes is set at an angle .theta. with respect to a reference line given by a straight line connecting a center of the gas inlet tube to a center of one of the semiconductor wafers, the angle .theta. being defined by 0.degree. < .theta. .ltoreq. 90.degree..Type: GrantFiled: December 18, 1991Date of Patent: October 12, 1993Assignees: Kabushiki Kaisha Toshiba, Tokyo Electron LimitedInventors: Shinji Miyazaki, Yuichi Mikata, Takahiko Moriya, Reiji Niino, Motohiko Nishimura