Abstract: The volatilization suppressing component according to the present disclosure has a metallic base material; and a laminated film having at least a first layer formed on a portion or the entirety of a surface of the metallic base material, and a second layer formed on the first layer, wherein the first layer is an adhesive layer between the metallic base material and the second layer, and the second layer is a protective layer for the first layer.

Abstract: A primary molded body having an angled connector that is integrally connected to an insulating annular body provided in a stator of a motor section, and that has a plurality of terminals extending along an axial direction of the motor section; a through-hole that is formed in the primary molded body and runs through the angled connector from an interior of the insulating annular body; a secondary molded body that is molded so as to cover the primary molded body; a secondary molded connector that is formed in the secondary molded body and covers the angled connector; and a connector opening that is formed in the secondary molded connector and communicates with the through-hole, wherein an outlet of the through-hole communicates with the connector opening.

Abstract: A primary molded body having an angled connector that is integrally connected to an insulating annular body provided in a stator of a motor section, and that has a plurality of terminals extending along an axial direction of the motor section; a through-hole that is formed in the primary molded body and runs through the angled connector from an interior of the insulating annular body; a secondary molded body that is molded so as to cover the primary molded body; a secondary molded connector that is formed in the secondary molded body and covers the angled connector; and a connector opening that is formed in the secondary molded connector and communicates with the through-hole, wherein an outlet of the through-hole communicates with the connector opening.

Abstract: It is an object of the present invention to provide a data switching method capable of impartially selecting a plurality of input ports by a simple circuit configuration. The data switching method according to the present invention includes an up-counter, a down-counter, a counter selecting circuit for selecting either of a counted value by the up-counter or a counted value by the down-counter, a port selecting circuit for selecting one of a plurality of input ports based on an output from the counter selecting circuit, and a buffer for accumulating a packet supplied from the input port selected by the port selecting circuit. The port selecting circuit alternately selects the up-counter and the down-counter to switch the ascending order and the descending order of the import priority of the input ports at every time the packet is imported, thereby impartially selecting each of the input ports.

Abstract: A communication LSI comprises a reception frame disassembling section 1 for receiving data from a network, a reception cell processing section 2 for processing a payload portion of the data disassembled in the reception frame disassembling section and outputting a result thereof to an ATM layer, a reception overhead memory 3 for storing an overhead portion of the data disassembled in the reception frame disassembling section, a receiving processor 4 for executing processes in the overhead portion by inputting desired data stored in the reception overhead memory when data is received, a status register 5 for storing a result processed in the receiving processor, a transmitting processor 6 for executing processes in the overhead portion by inputting the result stored in the status register when data is transmitted, a transmission overhead memory 7 for storing an output of the transmitting processor, a transmission cell processing section 8 for receiving data from an ATM layer, and a transmission frame assemblin

Abstract: A delay time measuring circuit includes a delay circuit for changing the delay times of first and second clock signals output to measure the delay time of an evaluated circuit according to an externally supplied control voltage, and a voltage controlled oscillator whose oscillation frequency is controlled by the same control voltage as that used for the delay circuit, and is constructed to measure the delay time of the evaluated circuit based on an output of the voltage controlled oscillator. Therefore, it is possible to precisely evaluate the operation speed of a circuit operating at high speed.

Abstract: A phase locked loop circuit, which is arranged for receiving a first signal having a given frequency and producing a second signal which has the same frequency and is synchronous with the first signal, comprises control voltage generating means for generating a control voltage responding to a phase difference and a frequency difference between the first and second signals, a voltage controlled oscillator containing a ring oscillator having a multiplicity of the rows of inverters for producing a frequency output which is primarily determined by the control voltage, and a quantity-of-rows changing means for automatically changing the quantity of the inverters rows in the ring oscillator according to the control voltage.

Abstract: A semiconductor memory having latch circuits, each of which is coupled to receive the potential of a bit line and which can operate, in response to a control signal, in either a through mode or a latch mode. In the through mode, the latch circuit outputs the potential of the bit line. In the latch mode, it latches this potential and then outputs it. The memory further comprises a dummy bit line and FETs. These FETs are provided at the intersections of the dummy bit line and all word lines of the memory. Hence, the dummy bit line is discharged whenever a word line has been selected. The latch circuits, which are provided in the output section of the memory, are set to the through mode when the dummy bit line is discharged to a predetermined potential.

Abstract: A CMOS logic circuit includes a first MOS transistor of one conductivity type and second and third MOS transistors of a conductivity type opposite to that of the first MOS transistor, the first to third MOS transistors being conducted in series with each other between first and second power source terminals. The gate of the first MOS transistor and the gate of one of the second and third MOS transistors commonly receive a input signal. The gate of the other of the second and third MOS transistors, serving as a correcting transistor, is connected to the first power source terminal. A series connecting point of the first and second MOS transistors serves as an output node. A channel size ratio W/L (where W is the channel width and L is the channel length) or an absolute value of a gate threshold voltage of the first MOS transistor is different from that of the correcting transistor.