Abstract: The present invention provides a heterocyclic compound having an orexin type 2 receptor agonist activity. A compound represented by the formula (I): wherein each symbol is as described in the specification, or a salt thereof, is useful as an agent for the prophylaxis or treatment of narcolepsy.

Abstract: In an in-vehicle network system (100), a parent control unit (10) and a child control unit (20) constitute a control unit. In the in-vehicle network system (100), a monitoring unit (70) acquires communication data being communicated between the parent control unit (10) and the child control unit (20) and flowing in an in-vehicle network (30) which connects the parent control unit (10) and the child control unit (20) to each other. The monitoring unit (70) diagnoses an abnormality in the parent control unit (10) based on the communication data acquired by the monitoring unit (70) and diagnostic data stored by a memory unit.

Abstract: An increase in the number of signal lines of a control apparatus for controlling devices of an automobile can be prevented and safety of the automobile can be secured. An in-vehicle communication system includes an input DHM that obtains device data from an input device, a BCM that generates control data for controlling an output device based on a value of the device data, and an output DHM that controls the output device according to the control data. The input DHM is composed of duplexed input control blocks, duplexed input shared memories, and an input NW control block. The BCM is composed of a BCM_NW control block, duplexed BCM shared memories for different intended uses, and duplexed arithmetic blocks. The output DHM is composed of an output NW control block, duplexed output shared memories, duplexed output control blocks, and a matching circuit.

Abstract: In an in-vehicle network system (100), a parent control unit (10) and a child control unit (20) constitute a control unit. In the in-vehicle network system (100), a monitoring unit (70) acquires communication data being communicated between the parent control unit (10) and the child control unit (20) and flowing in an in-vehicle network (30) which connects the parent control unit (10) and the child control unit (20) to each other. The monitoring unit (70) diagnoses an abnormality in the parent control unit (10) based on the communication data acquired by the monitoring unit (70) and diagnostic data stored by a memory unit.

Abstract: An increase in the number of signal lines of a control apparatus for controlling devices of an automobile can be prevented and safety of the automobile can be secured. An in-vehicle communication system includes an input DHM that obtains device data from an input device, a BCM that generates control data for controlling an output device based on a value of the device data, and an output DHM that controls the output device according to the control data. The input DHM is composed of duplexed input control blocks, duplexed input shared memories, and an input NW control block. The BCM is composed of a BCM_NW control block, duplexed BCM shared memories for different intended uses, and duplexed arithmetic blocks. The output DHM is composed of an output NW control block, duplexed output shared memories, duplexed output control blocks, and a matching circuit.

Abstract: A current controller for controlling a current supplied to a contact having an external power supply, includes a contact monitoring unit for monitoring the opening and the closing of the contact, a logical computing unit for analyzing a transition of the contact based on the monitoring result from the contact monitoring unit, and a short-circuit unit for short-circuiting the input route based on a direction from the logical computing unit. The logical computing unit turns on the short-circuit unit when the logical computing unit detects chattering at the opening of the contact, and turns off the short-circuit unit after the chattering ends at the closing of the contact.

Abstract: A multiprocessor apparatus includes a high speed processor coupled to a high speed bus, a low speed processor coupled to a low speed bus, a bus adapter for coupling between the high speed bus and the low speed bus, an operating system for determining as to at which processor application program is to be executed, and an activation controller for activating clock signal for the processor which executes the application program, based on the determination result of the operating system.

Abstract: A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.

Abstract: A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module 301 is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module 303 has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.

Abstract: A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module 301 is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module 303 has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.